Results 1 to 10 of about 271,965 (237)

Vacuum Inner Spacer to Improve Annealing Effect during Electro-Thermal Annealing of Nanosheet FETs

Micromachines, 2022
Electro-thermal annealing (ETA) in a MOSFET utilizes Joule heating. The high-temperature heat effectively cures gate dielectric damages induced by electrical stresses or ionizing radiation.
Dong-Hyun Wang, Khwang-Sun Lee, Jun-Young Park   +2 more
doaj   +2 more sources

Source/Drain Trimming Process to Improve Gate-All-Around Nanosheet Transistors Switching Performance and Enable More Stacks of Nanosheets

Micromachines, 2022
A new S/D trimming process was proposed to significantly reduce the parasitic RC of gate-all-around (GAA) nanosheet transistors (NS-FETs) while retaining the channel stress from epitaxy S/D stressors at most. With optimized S/D trimming, the 7-stage ring
Kun Chen, Jingwen Yang, Tao Liu, Dawei Wang, Min Xu, Chunlei Wu, Chen Wang, Saisheng Xu, David Wei Zhang, Wenchao Liu   +9 more
doaj   +2 more sources

Parasitics-Aware Quantum Transport Simulation of Stacked Si Nanosheet LGAA-nFETs for Sub-2 nm Node RF Applications [PDF]

Micromachines
This work presents a comprehensive quantum transport modeling and simulation framework to evaluate parasitic effects and radio frequency (RF) performance in stacked silicon (Si) nanosheet (NS) lateral gate-all-around (LGAA) nFETs targeting the sub-2 nm ...
Qi Shen, Shuo Zhang, Zhi-Fa Zhang, Wenchao Chen, Zekai Zhou, Sichao Du, Hao Xie, Wen-Yan Yin   +7 more
doaj   +2 more sources

Channel-engineered GAA FETs: From device to circuit perspective for Angstrom technology nodes [PDF]

Scientific Reports
This work presents a comprehensive device-to-circuit analysis of channel-engineered gate-all-around (GAA) FETs intended for advanced CMOS logic applications, namely the comb-shaped FET (C-FET) and inter-bridge FET (I-FET), benchmarked against a ...
Vakkalakula Bharath Sreenivasulu, Narasimhulu Thoti   +1 more
doaj   +2 more sources

High-efficient liquid exfoliation of 2D metal-organic framework using deep-eutectic solvents

Ultrasonics Sonochemistry, 2021
The exfoliation of bulk two-dimensional metal–organic framework (MOF) into few-layered nanosheets has attracted much attention recently. In this work, an environmental-friendly route has been developed for layered-MOF (MAMS-1) delamination using deep ...
Xinxin Sang, Dongyin Liu, Junling Song, Chan Wang, Xiangdao Nie, Gang Shi, Xiaofeng Xia, Caihua Ni, Dawei Wang   +8 more
doaj   +1 more source

Hydrazine High-Performance Oxidation and Sensing Using a Copper Oxide Nanosheet Electrocatalyst Prepared via a Foam-Surfactant Dual Template

Nanomaterials, 2022
This work demonstrates hydrazine electro-oxidation and sensing using an ultrathin copper oxide nanosheet (CuO-NS) architecture prepared via a versatile foam-surfactant dual template (FSDT) approach.
Etab M. Almutairi, Mohamed A. Ghanem, Abdulrahman Al-Warthan, Mufsir Kuniyil, Syed F. Adil   +4 more
doaj   +1 more source

The tuned selective catalytic reduction behaviors of NO over the Pt/CeO2 catalysts by preferentially exposing different facets of CeO2 supports

Catalysis Communications, 2022
For the Pt catalysts supported on CeO2 nanosheet (NS), nanopolyhedron (NP) and nanorod (NR) with preferentially exposed {100}, {111} and {110} facets, respectively, the NO conversion and N2 selectivity for NO + CO reaction at 100–250 °C exhibit the order
Kaiqiang Wang, Roujia Zhang, Songze Wu, Mengyin Chen, Jie Tang, Liming Zhao, Yubing Liu, Yining Fan   +7 more
doaj   +1 more source

Channel geometry-dependent threshold voltage and transconductance degradation in gate-all-around nanosheet junctionless transistors

AIP Advances, 2021
The gate-all-around (GAA) nanosheet (NS) junctionless transistor (JLT) is an attractive candidate for advanced technology nodes in CMOS scaling. Here, the channel width-dependent transconductance (gm) degradation and threshold voltage (Vth) shift of GAA ...
Dae-Young Jeon
doaj   +1 more source

A Comprehensive Technique Based on Machine Learning for Device and Circuit Modeling of Gate-All-Around Nanosheet Transistors

IEEE Open Journal of Nanotechnology, 2023
Machine learning (ML) is poised to play an important part in advancing the predicting capability in semiconductor device compact modeling domain. One major advantage of ML-based compact modeling is its ability to capture complex relationships and ...
Rajat Butola, Yiming Li, Sekhar Reddy Kola   +2 more
doaj   +1 more source

Strained Si Nanosheet pFET Based on SiC Strain Relaxed Buffer Layer for High Performance and Low Power Logic Applications

IEEE Access, 2023
The application of SiC-based strain-relaxed buffers (SRB) technology in gate-all-around (GAA) pMOS nanosheet transistors (NS-FETs) fabrication has been systematically investigated.
Kun Chen, Jingwen Yang, Chunlei Wu, Chen Wang, Min Xu, David Wei Zhang   +5 more
doaj   +1 more source