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PVS-NoC: Partial Virtual Channel Sharing NoC Architecture
2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2011A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead.
Khalid Latif 0002 +4 more
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2009 17th IEEE Symposium on High Performance Interconnects, 2009
In Chip Multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design.
Ahmed Abousamra +2 more
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In Chip Multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design.
Ahmed Abousamra +2 more
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Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
TDM (Time Division Multiplexing) is a well-known technique to provide QoS guarantees in NoCs. However, unused time slots commonly exist in TDM NoCs. In the paper, we propose a TDM highway technique which can enhance the slot utilization of TDM NoCs. A TDM highway is an express TDM connection composed of special buffer queues, called highway channels ...
Shaoteng Liu, Zhonghai Lu, Axel Jantsch
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TDM (Time Division Multiplexing) is a well-known technique to provide QoS guarantees in NoCs. However, unused time slots commonly exist in TDM NoCs. In the paper, we propose a TDM highway technique which can enhance the slot utilization of TDM NoCs. A TDM highway is an express TDM connection composed of special buffer queues, called highway channels ...
Shaoteng Liu, Zhonghai Lu, Axel Jantsch
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Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC
2013 Euromicro Conference on Digital System Design, 2013Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance.
Shaoteng Liu, Axel Jantsch, Zhonghai Lu
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Book Reviews: NoC, NoC ... Who's there?
IEEE Design and Test of Computers, 2006This is a review of Networks on Chips: Technology and Tools, by Giovanni De Micheli and Luca Benini. This comprehensive survey and integrated reference work on networks on chips (NoCs) offers both breadth in covering most of the major work in this area and depth in delving into all the related issues involved in designing advanced on-chip interconnect ...
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Evaluation of the bit error rate in Classic NoCs and Optical NoC
2018 30th International Conference on Microelectronics (ICM), 2018A system on chip (SoC) is composed of a large number of intellectual property (IP) blocks on the same silicon. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from those classic interconnections to optical ones becomes mandatory.
Moez Balti, Abderrazek Jemai
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A security monitoring service for NoCs
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, 2008As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-on-Chip (NoCs) have appeared as design strategy to cope with the rapid increase in complexity of Multiprocessor Systems-on-Chip (MPSoCs), but only recently research community have ...
L. FIORIN +2 more
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Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects.
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Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects.
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Intelligent NOC Hotspot Prediction
2011Hotspots are Network on-Chip (NoC) routers or modules which occasionally receive packetized traffic at a higher rate that they can process. This phenomenon reduces the performance of an NoC, especially in the case wormhole flow-control. Such situations may also lead to deadlocks, raising the need of a hotspot prevention mechanism.
Kakoulli, E. +5 more
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BHT-NoC: Blaming Hardware Trojans in NoC Routers
IEEE Design & Test, 2022Bharat Bisht, Shirshendu Das
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