Results 181 to 190 of about 153,973 (229)
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PVS-NoC: Partial Virtual Channel Sharing NoC Architecture
2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2011A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead.
Khlaid Latif +4 more
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Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC
JSTS:Journal of Semiconductor Technology and Science, 2016Today’s multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role.
M. Vijayaraj, K. Balamurugan
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Book Reviews: NoC, NoC ... Who's there?
IEEE Design and Test of Computers, 2006This is a review of Networks on Chips: Technology and Tools, by Giovanni De Micheli and Luca Benini. This comprehensive survey and integrated reference work on networks on chips (NoCs) offers both breadth in covering most of the major work in this area and depth in delving into all the related issues involved in designing advanced on-chip interconnect ...
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Proceedings of International Conference on Advances in Mobile Computing & Multimedia - MoMM '13, 2013
We describe MoM-NOCS, a Framework and a System that support communities with common interests in nature to capture and share multimedia observations of nature objects or events using mobile devices. The observations are automatically associated with contextual metadata that allow them to be visualized on top of 2D or 3D maps.
Chrisa Tsinaraki +3 more
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We describe MoM-NOCS, a Framework and a System that support communities with common interests in nature to capture and share multimedia observations of nature objects or events using mobile devices. The observations are automatically associated with contextual metadata that allow them to be visualized on top of 2D or 3D maps.
Chrisa Tsinaraki +3 more
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Proceedings of the 38th annual international symposium on Computer architecture, 2011
Today's chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized accelerators are anticipated in the near future. In this paper, we propose and evaluate technologies to enable networks-on-chip (NOCs) to support a thousand connected ...
Boris Grot +3 more
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Today's chip-level multiprocessors (CMPs) feature up to a hundred discrete cores, and with increasing levels of integration, CMPs with hundreds of cores, cache tiles, and specialized accelerators are anticipated in the near future. In this paper, we propose and evaluate technologies to enable networks-on-chip (NOCs) to support a thousand connected ...
Boris Grot +3 more
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ACM Transactions on Design Automation of Electronic Systems, 2017
Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform ...
Zoran Salcic +4 more
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Scalability and performance in multicore processors for embedded and real-time systems usually don't go well each with the other. Networks on Chip (NoCs) provide scalable execution platforms suitable for such kind of embedded systems. This article presents a NoC-based Heterogeneous Multi-Processor system, called NoC-HMP, which is a scalable platform ...
Zoran Salcic +4 more
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Proceedings of the 51st Annual Design Automation Conference, 2014
The rise of utilization wall limits the number of transistors that can be powered on in a single chip and results in a large region of dark silicon. While such phenomenon has led to disruptive innovation in computation, little work has been done for the Network-on-Chip (NoC) design.
Jia Zhan, Yuan Xie, Guangyu Sun
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The rise of utilization wall limits the number of transistors that can be powered on in a single chip and results in a large region of dark silicon. While such phenomenon has led to disruptive innovation in computation, little work has been done for the Network-on-Chip (NoC) design.
Jia Zhan, Yuan Xie, Guangyu Sun
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2006 International Symposium on Industrial Embedded Systems, 2006
The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex embedded applications performance requirements. Due to the increasing scale of embedded systems bus-based communication no longer meet bandwidth requirements and therefore networks-on-chip (NoC) are increasingly used to process ...
Riad Ben Mouhoub, Omar Hammami
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The Multiprocessor systems on chip are strongly emerging in various embedded systems to support dramatic growth of complex embedded applications performance requirements. Due to the increasing scale of embedded systems bus-based communication no longer meet bandwidth requirements and therefore networks-on-chip (NoC) are increasingly used to process ...
Riad Ben Mouhoub, Omar Hammami
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Intelligent NOC Hotspot Prediction
2011Hotspots are Network on-Chip (NoC) routers or modules which occasionally receive packetized traffic at a higher rate that they can process. This phenomenon reduces the performance of an NoC, especially in the case wormhole flow-control. Such situations may also lead to deadlocks, raising the need of a hotspot prevention mechanism.
Kakoulli, E. +5 more
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Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects.
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Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects.
openaire +2 more sources