Results 191 to 200 of about 36,603 (249)

Fault tolerant and quality of service aware routing algorithm based on priority technique for scalable network on chip architectures. [PDF]

Sci Rep
Yu X, Tang L, Mi J, Liu J, Long L.
europepmc   +1 more source

Prevalence and Clinico-Pathologic Profiles of Nonodontogenic Cysts of the Oral and Maxillofacial Region: A Multicentre Study. [PDF]

Int J Dent
Chantarangsu S, Kulthanaamondhita P, Dhanuthai K, Sappayatosok K, Klanrit P, Chamusri N, Aminishakib P, Hosseini SM, Singh R, Uddin J, Darling M.   +10 more
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Noc filozofów

Logos i Ethos, 2002
Workowski, Adam, Bobko, Aleksander, Szary, Stefan, Tarnowski, Karol, Pieńkowski, Marek, Kłoczowski, Jan, Bardel, Michał, Baczyński, Witold, Putyra, Łukasz, Kot, Elżbieta, Taylor, Charles, Mazurkiewicz, Łukasz, Hernas, Adam, Murzański, Piotr, Glinkowski, Piotr, Kot, Dobrosław, Piesko, Maria   +16 more
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PVS-NoC: Partial Virtual Channel Sharing NoC Architecture

2011 19th International Euromicro Conference on Parallel, Distributed and Network-Based Processing, 2011
A novel architecture aiming for ideal performance and overhead tradeoff, PVS-NoC (Partial VC Sharing NoC), is presented. Virtual channel (VC) is an efficient technique to improve network performance, while suffering from large silicon and power overhead.
Khalid Latif 0002, Amir-Mohammad Rahmani, Liang Guang, Tiberiu Seceleanu, Hannu Tenhunen   +4 more
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Analysis and Evaluation of Circuit Switched NoC and Packet Switched NoC

2013 Euromicro Conference on Digital System Design, 2013
Circuit switched NoC has, compared to packet switching, a longer setup time, guaranteed throughput and latency, higher clock frequency, lower HW complexity, and higher energy efficiency. Depending on packet size and throughput requirements they exhibit better or worse performance.
Shaoteng Liu, Axel Jantsch, Zhonghai Lu
openaire   +2 more sources

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A monitoring system for NoCs

Proceedings of the Third International Workshop on Network on Chip Architectures, 2010
In this paper, we propose and discuss a monitoring architecture for Networks-on-Chip (NoCs) that provides system information useful for helping designers in efficiently exploiting resources available in new complex Multiprocessor System-on-Chip (MPSoC) platforms, and in understanding their behavior. We focus on the analysis of the architectural details
Leandro Fiorin, PALERMO, GIANLUCA, SILVANO, CRISTINA   +2 more
openaire   +3 more sources