Results 201 to 210 of about 36,603 (249)
Some of the next articles are maybe not open access.
Effects of the NoC architecture in the performance of NoC-based MPSoCs
2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2014The goal of this work is to evaluate the impact of multiple Network-on-Chip (NoC) architectural parameters over the performance of applications running on Multiprocessors Systems-on-Chip (MPSoCs) using message passing as communication protocol. Nowadays, MPSoCs have so many constraints of performance that bus-based communications are not able to ...
Douglas R. G. Silva +2 more
openaire +1 more source
Performance Oriented Docket-NoC (Dt-NoC) Scheme for Fast Communication in NoC
JSTS:Journal of Semiconductor Technology and Science, 2016Today’s multi-core technology rapidly increases with more and more Intellectual Property cores on a single chip. Network-on-Chip (NoC) is an emerging communication network design for SoC. For efficient on-chip communication, routing algorithms plays an important role.
M. Vijayaraj, K. Balamurugan
openaire +1 more source
2013 27th International Conference on Advanced Information Networking and Applications Workshops, 2013
Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems, but also on high performance systems. In such systems, the data bandwidth requirements keeps increasing as the number of processing elements increases. Therefore, a Network-on-Chip (NoCs) communication architecture use to be preferred than a communication based on ...
José Miguel Montañana +2 more
openaire +1 more source
Multi-Processor Systems-on-Chip (MPSoCs) are increasingly popular in embedded systems, but also on high performance systems. In such systems, the data bandwidth requirements keeps increasing as the number of processing elements increases. Therefore, a Network-on-Chip (NoCs) communication architecture use to be preferred than a communication based on ...
José Miguel Montañana +2 more
openaire +1 more source
2009 17th IEEE Symposium on High Performance Interconnects, 2009
In Chip Multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design.
Ahmed Abousamra +2 more
openaire +1 more source
In Chip Multiprocessors (CMPs), on-chip interconnect carries data and coherence traffic exchanged between on chip cache banks. Reducing communication latency is critical for improving the performance of applications running on CMPs. Communication latency is affected by network design, cache organization, and application design.
Ahmed Abousamra +2 more
openaire +1 more source
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015
TDM (Time Division Multiplexing) is a well-known technique to provide QoS guarantees in NoCs. However, unused time slots commonly exist in TDM NoCs. In the paper, we propose a TDM highway technique which can enhance the slot utilization of TDM NoCs. A TDM highway is an express TDM connection composed of special buffer queues, called highway channels ...
Shaoteng Liu, Zhonghai Lu, Axel Jantsch
openaire +1 more source
TDM (Time Division Multiplexing) is a well-known technique to provide QoS guarantees in NoCs. However, unused time slots commonly exist in TDM NoCs. In the paper, we propose a TDM highway technique which can enhance the slot utilization of TDM NoCs. A TDM highway is an express TDM connection composed of special buffer queues, called highway channels ...
Shaoteng Liu, Zhonghai Lu, Axel Jantsch
openaire +1 more source
Evaluation of the bit error rate in Classic NoCs and Optical NoC
2018 30th International Conference on Microelectronics (ICM), 2018A system on chip (SoC) is composed of a large number of intellectual property (IP) blocks on the same silicon. However, as the number of IP blocks on a single chip and their performance continue to increase, a shift from those classic interconnections to optical ones becomes mandatory.
Moez Balti, Abderrazek Jemai
openaire +1 more source
Book Reviews: NoC, NoC ... Who's there?
IEEE Design and Test of Computers, 2006This is a review of Networks on Chips: Technology and Tools, by Giovanni De Micheli and Luca Benini. This comprehensive survey and integrated reference work on networks on chips (NoCs) offers both breadth in covering most of the major work in this area and depth in delving into all the related issues involved in designing advanced on-chip interconnect ...
openaire +1 more source
A security monitoring service for NoCs
Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, 2008As computing and communications increasingly pervade our lives, security and protection of sensitive data and systems are emerging as extremely important issues. Networks-on-Chip (NoCs) have appeared as design strategy to cope with the rapid increase in complexity of Multiprocessor Systems-on-Chip (MPSoCs), but only recently research community have ...
L. FIORIN +2 more
openaire +2 more sources
Proceedings of the 18th annual symposium on Integrated circuits and system design - SBCCI '05, 2005
Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects.
openaire +2 more sources
Summary form only given. Energy efficiency is a key concern in the design of advanced SoC platforms. In this talk we explore the delicate interplay between on-chip communication and power consumption. We move from state-of-the art communication fabrics (shared buses, crossbars), to advanced, "revolutionary" network-on-chip interconnects.
openaire +2 more sources
Intelligent NOC Hotspot Prediction
2011Hotspots are Network on-Chip (NoC) routers or modules which occasionally receive packetized traffic at a higher rate that they can process. This phenomenon reduces the performance of an NoC, especially in the case wormhole flow-control. Such situations may also lead to deadlocks, raising the need of a hotspot prevention mechanism.
Kakoulli, E. +5 more
openaire +3 more sources