Results 201 to 210 of about 1,624,283 (243)
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On upsizing length and noise margins
CAS 2013 (International Semiconductor Conference), 2013This paper revisits a transistor sizing method for CMOS gates, which relies on upsizing the length (L) and balancing the voltage transfer characteristics for maximizing the static noise margins (SNM's). It leads to highly reliable gates, able to operate over the whole voltage range.
Valeriu Beiu +4 more
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Marginal noise removal of document images
Proceedings of Sixth International Conference on Document Analysis and Recognition, 2002zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Kuo-Chin Fan +2 more
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Statistical analysis of static noise margins
2015 European Conference on Circuit Theory and Design (ECCTD), 2015This paper presents preliminary results of a statistical analysis of the SNM of inverters (as the basic element of any SRAM bit cell). Results are statistical meaningful as probabilities are calculated accurately, and should lead to more precise, faster, and better yield estimates. Comparisons with Monte Carlo simulations are supporting such claims.
Valeriu Beiu, Mihai Tache
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Series-voltage noise margin of CMOS
2000 10th Mediterranean Electrotechnical Conference. Information Technology and Electrotechnology for the Mediterranean Countries. Proceedings. MeleCon 2000 (Cat. No.00CH37099), 2002The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in a system, whilst still operating correctly. In this work the methods of determining the static and dynamic series-voltage noise margins and the obtained ...
Szabo, Aleksandar, Butković, Željko
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IEEE Circuits and Devices Magazine, 1994
Although CMOS technologies continue to dominate VLSI, advanced bipolar technologies are emerging as a viable alternative, thanks to improvements in circuit density and yield. These bipolar technologies are chiefly directed towards very high-speed applications, mostly in the form of emitter coupled logic (ECL) or current mode logic (CML) circuit ...
J.B. Foley, J.A.R. Bannister
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Although CMOS technologies continue to dominate VLSI, advanced bipolar technologies are emerging as a viable alternative, thanks to improvements in circuit density and yield. These bipolar technologies are chiefly directed towards very high-speed applications, mostly in the form of emitter coupled logic (ECL) or current mode logic (CML) circuit ...
J.B. Foley, J.A.R. Bannister
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A directional margin paradigm for noise suppression in face recognition
Journal of Visual Communication and Image Representation, 2021Abstract Convolutional neural networks (CNN) have achieved outstanding face recognition (FR) performance with increasing large-scale face datasets. With face dataset size grown, noisy data will inevitably increase, undoubtedly bringing difficulties to data cleaning.
Yang Zhou, Xun Gong 0002, Peng Yang 0007
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Noise-margin limitations on gallium-arsenide VLSI
IEEE Journal of Solid-State Circuits, 1988Two factors which limit the complexity of GaAs MESFET VLSI circuits are considered. Power dissipation sets an upper complexity limit for a given logic circuit implementation and thermal design. Uniformity of device characteristics and the circuit configuration determines the electrical functional yield.
Stephen I. Long, Mani Sundaram
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DSL loop qualification by using noise margin
2016 International Conference on Systems, Signals and Image Processing (IWSSIP), 2016This paper through the results of experimental research collected in real system under commercial exploitation investigates the significance of recommended ratio for one of physical layer parameter — SNR margin for the needs of loop qualification for IPTV over xDSL. At the beginning of this paper, a short definition and recommended value for SNR margin
Namir Skaljo +2 more
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Modeling the effect of ground bounce on noise margin
Proceedings., International Test Conference, 2002In integrated circuits, ground bounce is the voltage developed across the inductance of the power supply leads as a result of the current surge through switching gates. It causes distortion of circuit output waveforms that can interfere with testing.
Mary Sue Haydt +2 more
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A physically oriented model to quantify the dynamic noise margin [on-chip noise]
Proceedings of the 30th European Solid-State Circuits Conference, 2004The increase in on-chip noise has led to severe signal integrity problems in modern chip design. In a new approach, an analytical, physically motivated model is proposed which quantities the pulse transfer characteristic of a gate, aimed at quick circuit analysis.
Tobias Gemmeke, Tobias G. Noll
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