Results 211 to 220 of about 1,624,283 (243)
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Noise margins of bandpass filters
IEEE Transactions on Circuit Theory, 1973It is shown that if a bandpass filter is obtained from a prototype low-pass filter by the usual low-pass to bandpass transformation, the white-noise margin and the (1/f)^2 noise margin of the resulting filter will be identical to the white-noise margin of the prototype low-pass filter. A method for using this general result for evaluating some types of
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Noise Margin in Low Power SRAM Cells
2004Noise margin at read, at write and in stand-by is analyzed for the 6 transistor SRAM cell in a 0.18 μm process considering specific low power conditions such as low supply voltage and source-body biasing. These conditions reduce the noise margin. By using an asymmetrical cell design in which read is performed only on one of the two complementary bit ...
Stefan Cserveny +2 more
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Noise Margin Calculation in Multiple-Valued Logic
2020 10th International Conference on Computer and Knowledge Engineering (ICCKE), 2020Noise margin (NM) is an important concept in circuit design since noise is one of the major challenges for reliability. This subject is very critical in multiple-valued logic (MVL), where the entire voltage range is divided into several narrow zones. Ternary NMs are currently calculated based on a conventional definition.
Mehdi Takbiri +2 more
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Margin noise removal from printed document images
Proceeding of the workshop on Document Analysis and Recognition, 2012In this paper, we propose a technique for removing margin noise (both textual and non-textual noise) from scanned document images. We perform layout analysis to detect words, lines, and paragraphs in the document image. These detected elements are classified into text and non-text components on the basis of their characteristics (size, position, etc.).
Soumyadeep Dey +3 more
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Static series-voltage noise margins of CBL, CSL and CMOS
9th International Conference on Electronics, Circuits and Systems, 2003The concept of noise margin is very important in the design and application of digital logic circuits. Noise margin is the maximum spurious signal that can be accepted by the device when used in the system, whilst still operating correctly. In this work the static series-voltage noise margin of CBL (Current-Balanced Logic), CSL (Current-Steering Logic)
Butković, Željko, Szabo, Aleksandar
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Dynamic noise margins of MOS logic gates
IEEE International Symposium on Circuits and Systems, 2003Voltage transfer characteristics and static noise margins of basic NMOS and CMOS inverter connections are reviewed in terms of their logic dynamic performances and dynamic noise margins. The hysteresis phenomena, immunity to short pulse inputs, and noise margins depending upon both the capacitive load and the speed of the input signal are presented and
J.M. Zurada, Y.S. Joo, S.V. Bell
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Noise margins in digital integrated circuits
Proceedings of the IEEE, 1964Many integrated circuit logic gates, especially the complete monolithic type, operate at very low signal levels. For this reason, the sensitivity of such circuits to noise is very important. The general definition of noise margin leads to a discussion of dc and ac noise margins for a simple inverting gate, and specific test data of an RCTL gate.
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Noise Figure Rating for Marginal Oscillators
Review of Scientific Instruments, 1972The concept of noise figure is extended to marginal oscillators, devices which are commonly used in nuclear resonance experiments for detecting small changes in coil Q. This permits the absolute sensitivity of the circuit to be evaluated, without regard to extraneous factors, such as coil Q and sample material.
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Noise margin analysis for Pseudo-CMOS circuits
2016 7th International Conference on Computer Aided Design for Thin-Film Transistor Technologies (CAD-TFT), 2016Despite the large noise margin merit of pseudo- CMOS logic, its analytical model is absent. In this paper, we derive the static noise margin model for pseudo-CMOS (pseudo- D) logic circuits. Finally, we analyze the impact of design parameters on noise margin. Simulations show the modeling error is about 3%.
Qinghang Zhao +5 more
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The Static Noise Margin of SRAM cells
ESSCIRC '86: Twelfth European Solid-State Circuits Conference, 1986A simulation method is presented which makes it possible to analyze the stability of SRAM cells in terms of Static Noise Margin (SNM). With this method the effect of supply voltage reduction below the conventional 5V on the stability of resistor load (R-load) and full CMOS (6T) SRAM cells is analyzed.
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