Results 241 to 250 of about 128,528 (304)

In-Sensor-Memory Computing for Post-Von Neumann Intelligence: A Perspective. [PDF]

Nanomicro Lett
Tang H, Yu N, Min P, Guo R, Zhang G.
europepmc   +1 more source

Advances in neuroprostheses: interfaces, materials, and applications. [PDF]

Nano Converg
He E, Chen K, Liu S, Chen H, Xiao Y, Chen R, Tu P, Pan G, Lin P.   +8 more
europepmc   +1 more source

Fabrication of Stochastic Ni@PVP Nanowire Networks for Memristive Platforms. [PDF]

Polymers (Basel)
Lemos C, Dias C, Costa RS, Ventura J.
europepmc   +1 more source

Protonic nickelate device networks for spatiotemporal neuromorphic computing. [PDF]

Nat Nanotechnol
Zhou Y, Shah S, Dey T, Zhou Y, Kumar A, Sriram S, Guo S, Kumar S, Patel RK, Andrei EY, Cubukcu E, Ramanathan S, Kuzum D.   +12 more
europepmc   +1 more source

Element of non-volatile memory based on quantum dots

Вісник Харківського національногоуніверситету імені В.Н. Каразіна. Серія: Радіофізика та електроніка, 2018
K. H. Slabyi, A. H. Pashchenko
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Redesign the Memory Allocator for Non-Volatile Main Memory

ACM Journal on Emerging Technologies in Computing Systems, 2017
The non-volatile memory (NVM) has the merits of byte-addressability, fast speed, persistency and low power consumption, which make it attractive to be used as main memory. Commonly, user process dynamically acquires memory through memory allocators. However, traditional memory allocators designed with in-place data writes are not appropriate for the ...
Nong Xiao, Mingzhu Deng
exaly   +2 more sources

Dependable Non-Volatile Memory

Proceedings of the 11th ACM International Systems and Storage Conference, 2018
Recent advances in persistent memory (PM) enable fast, byte-addressable main memory that maintains its state across power cycling events. To survive power outages and prevent inconsistent application state, current approaches introduce persistent logs and require expensive cache flushes.
Arthur Martens, Rouven Scholz, Phil Lindow, Niklas Lehnfeld, Marc A. Kastner 0001, Rüdiger Kapitza   +5 more
openaire   +1 more source

A BIST Scheme for Non-Volatile Memories

Journal of Electronic Testing, 1998
A new BIST scheme for on-chip testing of non-volatile memories and based on signature analysis is presented. The signature of the whole memory, whose content can be changed selectively by the user, is dynamically self-learned by the memory and it is saved in a dedicated memory location.
OLIVO, Piero, DALPASSO M.
openaire   +4 more sources

In-memory file system for non-volatile memory

Proceedings of the 2013 Research in Adaptive and Convergent Systems, 2013
Current memory system hierarchy consists of cache memory, main memory, and secondary storage. Each level in this hierarchy has a different access speed to tolerate the long latency of the lower level but supports a large capacity as a whole memory system.
Hyunjun Kim, Joonwook Ahn, Sungtae Ryu, Jungsik Choi 0001, Hwansoo Han   +4 more
openaire   +1 more source