Results 201 to 210 of about 72,189,252 (249)
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An adaptive ISFET chemical imager chip
2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008A CMOS based ion sensitive chemical imager chip is presented for real time spatio- temporal monitoring of chemical activity. Ion-sensitive field effect transistors (ISFETs) implemented on an unmodified process (AMS 0.35 um) are used as the chemical input to the analogue circuits.
Pantelis Georgiou, Chris Toumazou
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An image signal multiprocessor on a single chip
IEEE Journal of Solid-State Circuits, 1990A digital image signal multiprocessor (ISMP), a multiprocessor version of a previous real-time image signal processor (RISP) for gray-level image processing, is discussed. It is composed of a main controller and four processor elements (PEs), which are programmable 12-b digital signal processors.
Masakatsu Maruyama +6 more
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Microfluidic ELISA: On-Chip Fluorescence Imaging
Biomedical Microdevices, 2004Fluorescent reactions of a heterogeneous sandwich enzyme-linked immunoassay (ELISA) in an all-PDMS [poly (dimethylsiloxane)] microfluidic device were detected using a cooled charge coupled device (CCD) camera interfaced with an epifluorescence microscope.
Edward, Eteshola, Michal, Balberg
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A Chip Set Core For Image Compression
IEEE 1990 International Conference on Consumer Electronics, 1990Two components for image compression which provide almost all the computational power required by today's efficient codecs for full motion image compression are presented. The first component computes 8*8 discrete-cosine transform and zigzag conversion of coefficient scanning for a pixel rate up to 27 MHz.
A. Artieri, O. Colavin
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Enhancement of the DNA microarray chip images
2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628), 2003In this paper a novel method of noise reduction in color images is presented. The new technique is capable of attenuating both impulsive and Gaussian noise, while preserving and even enhancing the sharpness of the image edges. Extensive simulations reveal that the new method outperforms significantly the standard techniques widely used in multivariate ...
Marek Szczepanski +3 more
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Artificial retina chips for image processing
Artificial Life and Robotics, 1997Artificial retina chips which can simultaneously sense and process real world images are described. The comparison between artificial retinal systems and conventional image processing systems is described. Variable sensitivity photodetection, which is an essential technology for the artificial retina chips, is introduced in detail.
Kazuo Kyuma +2 more
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Computational Imaging On a Chip
Frontiers in Optics 2013, 2013We review our progress on computational on-chip imaging that is based on partially-coherent digital in-line holography and its use in high-throughput microscopy and nanoscopy for biomedical applications.
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Imaging and Applied Optics, 2013
We review our recent progress on lensfree holographic on-chip microscopy techniques that are aimed at high-throughput imaging applications including 3D tracking of sperms.
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We review our recent progress on lensfree holographic on-chip microscopy techniques that are aimed at high-throughput imaging applications including 3D tracking of sperms.
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On-chip compression for HDR image sensors
2010 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2010An image compressing technique for High Dynamic Range (HDR) image sensors is introduced. Compression is performed in two steps: Pixel value coding optimization followed by DCT-based (Discrete Cosine Transform) compression. A floating point coding technique is first used with a common exponent shared between pixels of the same block, and then a DCT is ...
Fadoua Guezzi Messaoud +3 more
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A VLSI chip for wavelet image compression
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 2003We have designed a VLSI chip for wavelet image compression which is especially suited for CCD area sensors as well as for new technology approaches in CMOS image sensors. The design has been developed for maximal resolutions of 3072 times 2048 pixels. The used compression algorithm gives a PSNR (peak signal to noise ratio) of up to 39 dB at 1 bit/pixel
M. Schwarzenberg +3 more
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