Results 211 to 220 of about 72,189,252 (249)

CMOS chip for invasive ultrasound imaging

IEEE Journal of Solid-State Circuits, 1994
A very small transmit/receiver chip has been developed for use in an arterial ultrasonic imaging system. In this technique, a solid-state ultrasonic imaging head placed within a small medical catheter is used to provide high quality 360/spl deg/ images of arteries as small as 2 mm in diameter.
William C. Black, Douglas N. Stephens
openaire   +1 more source

A processor chip set on a 60K master image chip

1987 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1987
The implementation of two processor chips using a master image design methodology, implemented in a 1μm CMOS process will be reported. Containing 800K transistors the chips produce a typical delay of 0.8ns. In a 12.7×12.7mm array the average density is 0.65 square mils / transistor.
H. Schettler, G. Koetzle
openaire   +1 more source

Master Image Chip

1989
Structured (non-customized) chip designs use either the gate array or the master image approach. A gate array chip is divided into many cells of fixed size. Each cell contains the same logic gate (e. g. 3-way NAND gate). Multiple designs are implemented by a unique wiring of the basic cells with 2 (or more) layers of metal, using an identical ...
openaire   +1 more source

A Wireless Narrowband Imaging Chip for Capsule Endoscope

IEEE Transactions on Biomedical Circuits and Systems, 2010
This paper presents a dual-mode capsule gastrointestinal endoscope device. An endoscope combined with a narrowband image (NBI), has been shown to be a superior diagnostic tool for early stage tissue neoplasms detection. Nevertheless, a wireless capsule endoscope with the narrowband imaging technology has not been presented in the market up to now.
Lan-Rong Dung, Yin-Yi Wu
openaire   +2 more sources

A programmable image processing chip

ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187), 2002
A new high performance, programmable image processing chip targeted at video and HDTV applications is described. This was initially developed for image small object recognition but has much broader functional application including 1D and 2D FIR filtering as well as neural network computation. The core of the circuit is made up of an array of twenty one
E. LeRiguer, R. Woods, D. Ridge, J. McCanny   +3 more
openaire   +1 more source

A chip for realtime skeleting of images

IEEE Proceedings of the Custom Integrated Circuits Conference, 2002
A chip performing the special task of thinning (a common task in the field of image processing) is presented. The most important design decisions, the results, the layout, and the aspects of testability are described. The chip will be fabricated in a 2 mu m-CMOS process in standard-cell technique, using the VENUS system from the Siemens Company. It has
R.H. Rauscher, A.J. Maeder
openaire   +1 more source

Versatile Imaging Architecture Based on a System on Chip

2004
no ...
Chalimbaud, Pierre, Berry, François
openaire   +3 more sources

Image Processing On Reconfigurable System-on-Chip

Real-time image processing requires not only sophisticated heuristic algorithms customized for a particular application, but also needs substantial computational power to handle a massive quantity of input image data. Reconfigurable System-on- Chip (rSoC), a powerful method to harness the power of FPGA technology, is well suited to real-time image ...
openaire   +2 more sources

Molecular Imaging in Oncology: Current Impact and Future Directions

Ca-A Cancer Journal for Clinicians, 2022
Martin G. Pomper, Steven P Rowe
exaly  

Chipping Away at Imaging

Journal of the American College of Radiology, 2006
openaire   +2 more sources