Results 101 to 110 of about 6,647 (159)

Benchmarks for interconnect parasitic resistance and capacitance

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings., 2004
Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors ...
N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell   +7 more
openaire   +1 more source

Reducing the Effect of Parasitic Capacitance on the Micro-capacitive Humidity Sensor

2019 IEEE 14th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2019
It is the most important issue of how the effects of parasitic capacitance can be reduced during the development of micro-capacitive humidity sensor systems. For this purposes, in this paper, step-by-step optimizations were carried out through packaging and circuit to achieve a high-precision, high-stability, and high-repetition humidity sensor system.
Jihang Liu, Lidong Du, Yichen Pan, Yusi Zhu, Zhen Fang 0003, Zhan Zhao   +5 more
openaire   +1 more source

Development of a 3D capacitive gyroscope with reduced parasitic capacitance

Journal of Micromechanics and Microengineering, 2013
We present the development of a technological platform dedicated to 3D capacitive inertial sensors. The proof of concept will be made on a 3D gyroscope. The mobile structure is made within a 30 µm thick Si top layer of a SOI substrate, while poly-Si deposited on top of a sacrificial PSG layer serves as suspended top electrodes and connection wires ...
A Walther, B Desloges, C Lejuste, B Coster, P Audebert, J Willemin   +5 more
openaire   +1 more source

Effect of parasitic capacitance on DC SQUID performance

IEEE Transactions on Magnetics, 1991
The effect of parasitic capacitance Cp on DC SQUID characteristics and noise performance has been studied using a test structure consisting of 11 identical SQUID washers with Nb films of various widths covering the slit. The measured I-V characteristics are in good agreement with simulations based on a simple lumped circuit model. The energy resolution
Ryhänen, Tapani, Cantor, Robin, Drung, Dietmar, Koch, Hans, Seppä, Heikki   +5 more
openaire   +1 more source

Parasitic capacitance removal with an embedded ground layer

Eurocon 2013, 2013
One of the major goals in designing integrated EMI filters is to improve their high-frequency characteristics. To achieve this, special technologies need to be developed, including the mechanism for suppression of the equivalent parallel capacitance (EPC). In previous studies, there were several methods used to reduce this parasitic capacitance, but in
Claudia Hebedean, Calin Munteanu, Adina Racasan, Claudia Pacurar   +3 more
openaire   +1 more source

Introduction of parasitic capacitance and methods of reducing its capacitance

Applied and Computational Engineering
This paper aims to introduce some basic knowledge of parasitic capacitors and how to reduce the impact of parasitic capacitors in theory and in practice. In the production and processing and daily life, people will be more or less to the use of capacitors.
Changqing Bao, Hongjia Zhu, Jiayu Liu
openaire   +1 more source

Measurements and extractions of parasitic capacitances in ulsi layouts

IEEE Transactions on Electron Devices, 2003
This paper deals with the extraction of parasitic capacitances of interconnects in submicron layouts. It is well known that, in integrated circuits, the signal delay due to interconnects is comparable to that of gates. This aspect becomes particularly important, for example, during the design of clock trees in high-speed applications.
BRAMBILLA, ANGELO MAURIZIO, MAFFEZZONI, PAOLO, L. Bortesi, L. Vendrame   +3 more
openaire   +1 more source

Design of a Capacitance Measurement Circuit with Input Parasitic Capacitance Elimination

2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM), 2020
This paper proposes a capacitance sensing circuit which converts the change of input capacitance into digital code as output signal. The whole CDC circuit is designed using SMIC 0.18\ \mu\mathrm{m}$ CMOS process technology in cadence. It contains an AFE circuit and an advanced single-slop ADC circuit.
Dantong Wu, Chunqi Qian, Xiaoyu Zhang, Zheng Wang, Xu Liu   +4 more
openaire   +1 more source

Parasitic Capacitances and Their Linear Approximation

1990
In Chapters 4, 5 and 6, an efficient numerical technique for computing the parasitic capacitances in VLSI circuits has been presented. Although the numerical techniques are powerful, they still require a great amount of computer resources for complicated geometries. It is expensive to handle a large layout with them.
Patrick Dewilde, Zhen-Qui Ning
openaire   +1 more source

Resonant clocking using distributed parasitic capacitance

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., 2004
A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies.
Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown   +4 more
openaire   +1 more source