Results 241 to 250 of about 46,362 (283)

Low-κ Extension Doping for High-Performance Carbon Nanotube Transistors: Toward High-Speed, Energy-Efficient Electronics. [PDF]

Adv Sci (Weinh)
Chiu HY, Chou CH, Wu GZ, Huang HY, Liu BH, Kei CC, Chien CH.   +6 more
europepmc   +1 more source

A Compact L-Band Reconfigurable Dual-Mode Patch Filter. [PDF]

Micromachines (Basel)
Sheta AF, Alkanhal MAS, Elshafiey I.
europepmc   +1 more source

A Stepped-Spacer FinFET Design for Enhanced Device Performance in FPGA Applications. [PDF]

Micromachines (Basel)
Zareiee M, Mehrad M, Tawfik A.
europepmc   +1 more source

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Development of a 3D capacitive gyroscope with reduced parasitic capacitance

Journal of Micromechanics and Microengineering, 2013
We present the development of a technological platform dedicated to 3D capacitive inertial sensors. The proof of concept will be made on a 3D gyroscope. The mobile structure is made within a 30 µm thick Si top layer of a SOI substrate, while poly-Si deposited on top of a sacrificial PSG layer serves as suspended top electrodes and connection wires ...
A Walther, B Desloges, C Lejuste, B Coster, P Audebert, J Willemin   +5 more
openaire   +1 more source

Efficient extraction of metal parasitic capacitances

Proceedings International Conference on Microelectronic Test Structures, 2002
Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed.
G.J. Gaston, I.G. Daniels
openaire   +1 more source

Parasitic capacitance effects of planar resistors

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989
The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects.
S.N. Demurie, G. De Mey
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Parasitic Capacitances in Double Gate MOSFET

2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward.
Viranjay M. Srivastava, null Priyank, Sharad P. Singh, G. Singh   +3 more
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Design of a Capacitance Measurement Circuit with Input Parasitic Capacitance Elimination

2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM), 2020
This paper proposes a capacitance sensing circuit which converts the change of input capacitance into digital code as output signal. The whole CDC circuit is designed using SMIC 0.18\ \mu\mathrm{m}$ CMOS process technology in cadence. It contains an AFE circuit and an advanced single-slop ADC circuit.
Dantong Wu, Chunqi Qian, Xiaoyu Zhang, Zheng Wang, Xu Liu   +4 more
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Resonant clocking using distributed parasitic capacitance

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., 2004
A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies.
A.J. Drake, K.J. Nowka, T.Y. Nguyen, J.L. Burns, R.B. Brown   +4 more
openaire   +1 more source