Results 251 to 260 of about 46,362 (283)

Parasitic capacitance modeling for multilevel interconnects

Asia-Pacific Conference on Circuits and Systems, 2003
The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be ...
S. Tani, Y. Uchida, M. Furuie, S. Tsukiyama, null BuYeol Lee, S. Nishi, Y. Kubota, I. Shirakawa, S. Imai   +8 more
openaire   +1 more source

Parasitic capacitance of submicrometer MOSFET's

IEEE Transactions on Electron Devices, 1999
We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer ...
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FCAP2: Parasitic Capacitance/Resistance Simulator

1986
To simulate the parasitic capacitance/resistance, it is necessary to solve the Poisson (or Laplace) equation in at least two dimensions with arbitrary input geometry.
Kit Man Cham, Soo-Young Oh, Daeje Chin, John L. Moll   +3 more
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Research on temperature characteristic of parasitic capacitance in MEMS capacitive accelerometer

Sensors and Actuators A: Physical, 2019
Abstract In MEMS capacitive accelerometer, parasitic capacitance is a serious problem, and its change over temperature would deteriorate performance of MEMS accelerometer. Yet, the temperature characteristic of parasitic capacitance hasn’t got enough research. In this work, the parasitic capacitance and its effect on bias drift are quantificationally
Xianshan Dong, Qinwen Huang, Wei Xu, Bin Tang, Shaohua Yang, Junhua Zhu, Yunfei En   +6 more
openaire   +1 more source

Parasitic Capacitances on Planar Coil

Journal of Electromagnetic Waves and Applications, 2009
In this paper, a formalism to calculate parasitic capacitances on planar coils is proposed. This analysis is based on experimental results through RL circuits where the inductors are coils built in...
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Capacitive biosensor based on vertically paired electrode with controlled parasitic capacitance

Sensors and Actuators B: Chemical, 2018
Abstract A capacitive biosensor based on vertically paired electrodes with controlled parasitic capacitance is presented to improve the sensitivity of capacitive measurement. The vertically paired electrodes were fabricated with a parylene film as a dielectric layer, with the distance between the electrodes less than hundreds of nanometer.
Ga-Yeon Lee, Jun-Hee Park, Young Wook Chang, Min-Jung Kang, Sungbo Cho, Jae-Chul Pyun   +5 more
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Effect of parasitic capacitance on DC SQUID performance

IEEE Transactions on Magnetics, 1991
The effect of parasitic capacitance Cp on DC SQUID characteristics and noise performance has been studied using a test structure consisting of 11 identical SQUID washers with Nb films of various widths covering the slit. The measured I-V characteristics are in good agreement with simulations based on a simple lumped circuit model. The energy resolution
Ryhänen, Tapani, Cantor, Robin, Drung, Dietmar, Koch, Hans, Seppä, Heikki   +5 more
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Introduction of parasitic capacitance and methods of reducing its capacitance

Applied and Computational Engineering
This paper aims to introduce some basic knowledge of parasitic capacitors and how to reduce the impact of parasitic capacitors in theory and in practice. In the production and processing and daily life, people will be more or less to the use of capacitors.
Changqing Bao, Hongjia Zhu, Jiayu Liu
openaire   +1 more source

VLSI parasitic capacitance determination by flux tubes

IEEE Circuits & Systems Magazine, 1982
A two-dimensional numerical approach for calculating capacitance between two conductors through different dielectrics is developed. The approach uses Laplace's equation in two dimensions to determine potentials on a grid system between the conductors.
W. H. Dierking, J. D. Bastian
openaire   +1 more source

Parasitic Capacitance Analysis in Short Channel GaN MIS-HEMTs

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021
Gate-to-channel coupling capacitance behavior on GaN-HEMT with recessed MIS-gate was analyzed combining experimental data and 2D-simulations. A new protocol to discriminate the contribution of the active channel and of the different coupling parasitic capacitances on a C-V curve of a GaN MIS-HEMT is proposed.
Kammeugne, R. Kom, Leroux, C., Frutuoso, T. Mota, Cluzel, J., Vauche, L., Le Royer, C., Gwoziecki, R., Garros, X., Gaillard, F., Charles, M., Bano, Edwige, Ghibaudo, Gérard   +11 more
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