Results 251 to 260 of about 159,072 (298)
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Resonant clocking using distributed parasitic capacitance
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., 2004A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies.
Alan J. Drake +4 more
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Parasitic Capacitances on Planar Coil
Journal of Electromagnetic Waves and Applications, 2009In this paper, a formalism to calculate parasitic capacitances on planar coils is proposed. This analysis is based on experimental results through RL circuits where the inductors are coils built in...
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A simple analog interface for capacitive sensor with offset and parasitic capacitance
2015 Annual IEEE India Conference (INDICON), 2015In this paper, a simple but efficient analog interface circuit for floating capacitive sensor is presented. In most of the capacitive sensor, the offset and parasitic components are associated with the sensor and varies with the measurand. In these sensors, the change in the sensor capacitance due to measurand can be very small but having a relatively ...
Shahid Malik +5 more
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Introduction of parasitic capacitance and methods of reducing its capacitance
Applied and Computational EngineeringThis paper aims to introduce some basic knowledge of parasitic capacitors and how to reduce the impact of parasitic capacitors in theory and in practice. In the production and processing and daily life, people will be more or less to the use of capacitors.
Changqing Bao, Hongjia Zhu, Jiayu Liu
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Parasitic capacitance effects of planar resistors
IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects.
S.N. Demurie, G. De Mey
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Efficient extraction of metal parasitic capacitances
Proceedings International Conference on Microelectronic Test Structures, 2002Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed.
G.J. Gaston, I.G. Daniels
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Parasitic Capacitances in Double Gate MOSFET
2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward.
Viranjay M. Srivastava +3 more
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FCAP2: Parasitic Capacitance/Resistance Simulator
1986To simulate the parasitic capacitance/resistance, it is necessary to solve the Poisson (or Laplace) equation in at least two dimensions with arbitrary input geometry.
Kit Man Cham +3 more
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AMPLIFIER WITH PARASITIC CAPACITANCE NEUTRALIZATION
2023ADNAN MUHAMMAD, GUAN XIANG
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