Results 231 to 240 of about 2,130 (264)
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IEEE Electron Device Letters, 2017
In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently.
Sourabh Khandelwal +4 more
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In this letter, we present a compact model and analyze the impact of key parameters on negative capacitance FinFET (NC-FinFET) device operation. The developed model solves FinFET device electrostatics and Landau–Khalatnikov equations self-consistently.
Sourabh Khandelwal +4 more
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Minimize the delay of parasitic capacitance and modeling in RLC circuit
Proceedings of the 2009 International Conference on Hybrid Information Technology, 2009This paper shows that how to minimize the delay. We changed several elements to minimize the delay in the circuit. Simulation results show the best effect when the value of parasitic capacitance is changed. We found eligible point by simulating Parasitic Capacitance case by case based and proved it. Types of case are Elmore delay, Interconnection delay,
Dukgwon Lee +6 more
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Fast and accurate parasitic capacitance models for layout-aware
Proceedings of the 41st annual Design Automation Conference, 2004Considering layout effects early in the analog design process is becoming increasingly important. We propose techniques for estimating parasitic capacitances based on look-up tables and multi-variate linear interpolation. These models enable fast and accurate estimation of parasitic capacitances and are very suitable for use in a synthesis flow.
Anuradha Agarwal +3 more
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Accurate estimation of parasitic capacitances in analog circuits
Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004Anuradha Agarwal +3 more
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Calculation and modelling of transformer parasitic capacitance
IET Conference Proceedings, 2022W. Guo, J. Yang, R. Li
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Hierarchical Circuit Extraction with Detailed Parasitic Capacitance
20th Design Automation Conference Proceedings, 1983Gary M. Tarolli, William J. Herman
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Compact DC and Quasi-Static Capacitances Modeling of a-Si:H TFTs, Including Parasitic Capacitances
IEEE Transactions on Electron Devices, 2021François Lime +2 more
exaly
Analytical estimation of parasitic capacitances in high‐voltage switching transformers
IET Power Electronics, 2020Hamid Reza Mohammadi, Abbas Ketabi
exaly