Results 211 to 220 of about 2,141 (267)

Design of a Capacitance Measurement Circuit with Input Parasitic Capacitance Elimination

2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM), 2020
This paper proposes a capacitance sensing circuit which converts the change of input capacitance into digital code as output signal. The whole CDC circuit is designed using SMIC 0.18\ \mu\mathrm{m}$ CMOS process technology in cadence. It contains an AFE circuit and an advanced single-slop ADC circuit.
Dantong Wu, Chunqi Qian, Xiaoyu Zhang, Zheng Wang, Xu Liu   +4 more
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Parasitic capacitance of submicrometer MOSFET's

IEEE Transactions on Electron Devices, 1999
We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer ...
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Parasitic Capacitances and Their Linear Approximation

1990
In Chapters 4, 5 and 6, an efficient numerical technique for computing the parasitic capacitances in VLSI circuits has been presented. Although the numerical techniques are powerful, they still require a great amount of computer resources for complicated geometries. It is expensive to handle a large layout with them.
Patrick Dewilde, Zhen-Qui Ning
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Resonant clocking using distributed parasitic capacitance

Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003., 2004
A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies.
Alan J. Drake, Kevin J. Nowka, Tuyet Nguyen, Jeffrey L. Burns, Richard B. Brown   +4 more
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A simple analog interface for capacitive sensor with offset and parasitic capacitance

2015 Annual IEEE India Conference (INDICON), 2015
In this paper, a simple but efficient analog interface circuit for floating capacitive sensor is presented. In most of the capacitive sensor, the offset and parasitic components are associated with the sensor and varies with the measurand. In these sensors, the change in the sensor capacitance due to measurand can be very small but having a relatively ...
Shahid Malik, Tarikul Islam, Kaushal Kishore, Krishan Kumar, S.A. Akbar, B.A. Botre   +5 more
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Research on temperature characteristic of parasitic capacitance in MEMS capacitive accelerometer

Sensors and Actuators A: Physical, 2019
Abstract In MEMS capacitive accelerometer, parasitic capacitance is a serious problem, and its change over temperature would deteriorate performance of MEMS accelerometer. Yet, the temperature characteristic of parasitic capacitance hasn’t got enough research. In this work, the parasitic capacitance and its effect on bias drift are quantificationally
Xianshan Dong, Qinwen Huang, Wei Xu, Bin Tang, Shaohua Yang, Junhua Zhu, Yunfei En   +6 more
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Parasitic Capacitances on Planar Coil

Journal of Electromagnetic Waves and Applications, 2009
In this paper, a formalism to calculate parasitic capacitances on planar coils is proposed. This analysis is based on experimental results through RL circuits where the inductors are coils built in...
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Parasitic Capacitances in Double Gate MOSFET

2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward.
Viranjay M. Srivastava, null Priyank, Sharad P. Singh, G. Singh   +3 more
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Parasitic capacitance effects of planar resistors

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989
The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects.
S.N. Demurie, G. De Mey
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Efficient extraction of metal parasitic capacitances

Proceedings International Conference on Microelectronic Test Structures, 2002
Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed.
G.J. Gaston, I.G. Daniels
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