Results 201 to 210 of about 2,130 (264)

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices. [PDF]

Sci Rep
Kubanek D, Shadrin A, Seda P, Dvorak J, Jerabek J, Kledrowetz V, Christie C, Freeborn TJ, Ushakov PA.   +8 more
europepmc   +1 more source

A Compact Low-Power Chopper Low Noise Amplifier for High Density Neural Front-Ends. [PDF]

Sensors (Basel)
Fava A, Centurelli F, Monsurrò P, Scotti G.   +3 more
europepmc   +1 more source

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Compensation of Parasitic Capacitances in Broadband Filters

IEEE Transactions on Circuit Theory, 1967
Methods are presented to anticipate the effect of the coils parasitic capacitances in the implementation of broadband filters. The case of uniform parasitic capacitances leads to a process in some respect analogous to the classical predistortion theory for losses: the compensation problem can be solved by operating solely on the transmittance function.
J Neirynck
exaly   +2 more sources

Stability of a circuit with parasitic capacitances

Proceedings of ISCAS'95 - International Symposium on Circuits and Systems, 2002
A novel algorithm which is based on the linear programming technique is proposed to test the stability property of a circuit. This algorithm is efficient and non-Lyapunov equation based. Parasitic capacitances which may de-stabilize a circuit can be located.
Shek-Wai Ng, Yim-Shu Lee, C. K. Tse, Simon C. Wong   +3 more
openaire   +1 more source

Parasitic capacitance modeling for multilevel interconnects

Asia-Pacific Conference on Circuits and Systems, 2003
The problem of calculating parasitic capacitance between interconnects is investigated with the main theme focused on deriving approximate expressions for calculating parasitic capacitance between two crossing interconnects. The interconnects are divided into a few basic coupling regions, in such a way that the capacitance in a region can be ...
Sadahiro Tani, Yoshihiro Uchida, Makoto Furuie, Shuji Tsukiyama, BuYeol Lee, Shuji Nishi, Yasushi Kubota, Isao Shirakawa, Shigeki Imai   +8 more
openaire   +1 more source

Benchmarks for interconnect parasitic resistance and capacitance

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings., 2004
Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors ...
N. S. Nagaraj, Tom Bonifield, Abha Singh, Frank Cano, Usha Narasimha, Mak Kulkarni, Poras T. Balsara, Cyrus D. Cantrell   +7 more
openaire   +1 more source

Reducing the Effect of Parasitic Capacitance on the Micro-capacitive Humidity Sensor

2019 IEEE 14th International Conference on Nano/Micro Engineered and Molecular Systems (NEMS), 2019
It is the most important issue of how the effects of parasitic capacitance can be reduced during the development of micro-capacitive humidity sensor systems. For this purposes, in this paper, step-by-step optimizations were carried out through packaging and circuit to achieve a high-precision, high-stability, and high-repetition humidity sensor system.
Jihang Liu, Lidong Du, Yichen Pan, Yusi Zhu, Zhen Fang 0003, Zhan Zhao   +5 more
openaire   +1 more source