Results 221 to 230 of about 2,130 (264)

Parasitic capacitance of submicrometer MOSFET's

IEEE Transactions on Electron Devices, 1999
We systematically investigated the dependence of parasitic capacitance on gate length, gate electrode thickness, and gate oxide thickness using a 2-D device simulator. We showed that the model commonly used for parasitic capacitance is not accurate and also showed that more the rigorous model proposed by Kamchouchi should be used for submicrometer ...
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Parasitic Capacitances on Planar Coil

Journal of Electromagnetic Waves and Applications, 2009
In this paper, a formalism to calculate parasitic capacitances on planar coils is proposed. This analysis is based on experimental results through RL circuits where the inductors are coils built in...
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Parasitic Capacitances in Double Gate MOSFET

2010 International Conference on Recent Trends in Information, Telecommunication and Computing, 2010
Parasitic components of a MOSFET are mainly responsible for the intrinsic delay of logic gates, and they can be modelled with fairly high accuracy for gate delay estimation. The extraction of transistor parasitic from physical structure (mask layout) is also fairly straight forward.
Viranjay M. Srivastava, null Priyank, Sharad P. Singh, G. Singh   +3 more
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Parasitic capacitance effects of planar resistors

IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 1989
The intrinsic capacitance of a planar resistor in a hybrid circuit is discussed. Basic theory is outlined to model the self-capacitance effect of resistive layers. A perturbation method is derived where the zeroth order accounts for the pure resistive effects and the first-order perturbation deals with the capacitive effects.
S.N. Demurie, G. De Mey
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Efficient extraction of metal parasitic capacitances

Proceedings International Conference on Microelectronic Test Structures, 2002
Accurate extraction of parasitic capacitances associated with fine pitch metallisation layers is essential in the design of ULSI ICs. This paper reports on investigation of the impact of test structure design on extracted values for inter-layer and intra-layer capacitances; the influence of topography is also reviewed.
G.J. Gaston, I.G. Daniels
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Minimization of parasitic capacitances in VMOS transistors

1976 International Electron Devices Meeting, 1976
Process techniques for the reduction of parasitic capacitances in VMOS transistors (1) have been developed. Significant reductions in gate to drain overlap capacitance and side wall component of the junction capacitance have been achieved for a high performance VMOS process.
I.S. Bhatti, T.J. Rodgers, J.R. Edwards
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FCAP2: Parasitic Capacitance/Resistance Simulator

1986
To simulate the parasitic capacitance/resistance, it is necessary to solve the Poisson (or Laplace) equation in at least two dimensions with arbitrary input geometry.
Kit Man Cham, Soo-Young Oh, Daeje Chin, John L. Moll   +3 more
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Parasitic influences in a capacitive transducer behavior

Proceedings of the 2011 34th International Spring Seminar on Electronics Technology (ISSE), 2011
The most common parasitic effects involved in a capacitive measurement process are the fringing phenomenon, the error due to unparallel armatures, the capillarity phenomenon, the temperature and humidity influence and the electrical parasitic capacitances induced by the PCB connection traces.
Vlad Bande, Ioan Ciascai, Dan Pitica
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Capacitive biosensor based on vertically paired electrode with controlled parasitic capacitance

Sensors and Actuators B: Chemical, 2018
Abstract A capacitive biosensor based on vertically paired electrodes with controlled parasitic capacitance is presented to improve the sensitivity of capacitive measurement. The vertically paired electrodes were fabricated with a parylene film as a dielectric layer, with the distance between the electrodes less than hundreds of nanometer.
Ga-Yeon Lee, Jun-Hee Park, Young Wook Chang, Min-Jung Kang, Sungbo Cho, Jae-Chul Pyun   +5 more
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Impact of parasitic capacitances on the performance of SAR ADCs based on capacitive arrays

2010 First IEEE Latin American Symposium on Circuits and Systems (LASCAS), 2010
This paper analyzes the effect of parasitic capacitances on the performance of SAR ADCs based on capacitive arrays, usually employed in biomedical sensors due to their low-power consumption. The paper compares the most common architectures employed for capacitive DACs, analyzing the different effects that parasitic capacitances have on their linearity ...
Alberto Rodriguez-Perez, J. Antonio Rodriguez-Rodriguez, Fernando Medeiro, Manuel Delgado-Restituto   +3 more
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