Results 261 to 270 of about 19,412 (287)

Effect of parasitic capacitance on DC SQUID performance

IEEE Transactions on Magnetics, 1991
The effect of parasitic capacitance Cp on DC SQUID characteristics and noise performance has been studied using a test structure consisting of 11 identical SQUID washers with Nb films of various widths covering the slit. The measured I-V characteristics are in good agreement with simulations based on a simple lumped circuit model. The energy resolution
Ryhänen, Tapani, Cantor, Robin, Drung, Dietmar, Koch, Hans, Seppä, Heikki   +5 more
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Introduction of parasitic capacitance and methods of reducing its capacitance

Applied and Computational Engineering
This paper aims to introduce some basic knowledge of parasitic capacitors and how to reduce the impact of parasitic capacitors in theory and in practice. In the production and processing and daily life, people will be more or less to the use of capacitors.
Changqing Bao, Hongjia Zhu, Jiayu Liu
openaire   +1 more source

VLSI parasitic capacitance determination by flux tubes

IEEE Circuits & Systems Magazine, 1982
A two-dimensional numerical approach for calculating capacitance between two conductors through different dielectrics is developed. The approach uses Laplace's equation in two dimensions to determine potentials on a grid system between the conductors.
W. H. Dierking, J. D. Bastian
openaire   +1 more source

Parasitic Capacitance Analysis in Short Channel GaN MIS-HEMTs

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021
Gate-to-channel coupling capacitance behavior on GaN-HEMT with recessed MIS-gate was analyzed combining experimental data and 2D-simulations. A new protocol to discriminate the contribution of the active channel and of the different coupling parasitic capacitances on a C-V curve of a GaN MIS-HEMT is proposed.
Kammeugne, R. Kom, Leroux, C., Frutuoso, T. Mota, Cluzel, J., Vauche, L., Le Royer, C., Gwoziecki, R., Garros, X., Gaillard, F., Charles, M., Bano, Edwige, Ghibaudo, Gérard   +11 more
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Parasitic Capacitances and Their Linear Approximation

1990
In Chapters 4, 5 and 6, an efficient numerical technique for computing the parasitic capacitances in VLSI circuits has been presented. Although the numerical techniques are powerful, they still require a great amount of computer resources for complicated geometries. It is expensive to handle a large layout with them.
Patrick Dewilde, Zhen-Qui Ning
openaire   +1 more source

Benchmarks for interconnect parasitic resistance and capacitance

Fourth International Symposium on Quality Electronic Design, 2003. Proceedings., 2004
Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors ...
N.S. Nagaraj, T. Bonifield, A. Singh, F. Cano, U. Narasimha, M. Kulkarni, P. Balsara, C. Cantrell   +7 more
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Minimization of parasitic capacitances in VMOS transistors

1976 International Electron Devices Meeting, 1976
Process techniques for the reduction of parasitic capacitances in VMOS transistors (1) have been developed. Significant reductions in gate to drain overlap capacitance and side wall component of the junction capacitance have been achieved for a high performance VMOS process.
I.S. Bhatti, T.J. Rodgers, J.R. Edwards
openaire   +1 more source

Parasitic capacitances of Dual-K spacer FinFET

2016 Conference on Emerging Devices and Smart Systems (ICEDSS), 2016
This paper presents the impact of gate underlap length and high-k spacer width on the parasitic capacitances of nanoscale Dual-K spacer FinFET. It was found that the optimum gate underlap length can considerably reduce the parasitic capacitances. Also, the impact of abrupt doping profile on the parasitic capacitance of the device is discussed.
Shilpa Bisnoi, Sudeb Dasgupta
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Investigating parasitic capacitance cancellation for EMI suppression

2009 IEEE Vehicle Power and Propulsion Conference, 2009
This paper begins with the review of different parasitic capacitance cancellation techniques. The effectiveness of different cancellation techniques is discussed. The critical parameters and constraints for each cancellation technique are identified. The cancellation techniques are then applied to different applications based on their characteristics ...
null Shuo Wang, F.C. Lee
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Parasitic influences in a capacitive transducer behavior

Proceedings of the 2011 34th International Spring Seminar on Electronics Technology (ISSE), 2011
The most common parasitic effects involved in a capacitive measurement process are the fringing phenomenon, the error due to unparallel armatures, the capillarity phenomenon, the temperature and humidity influence and the electrical parasitic capacitances induced by the PCB connection traces.
Vlad Bande, Ioan Ciascai, Dan Pitica
openaire   +1 more source