Results 91 to 100 of about 22,805 (227)
DESIGN OF LOW POWER PHASE LOCKED LOOP (PLL) USING 45NM VLSI TECHNOLOGY
, 2023 Power has become one of the most important paradigms of design convergence for multi gigahertz communication systems such as optical data links, wireless products, microprocessor & ASIC/SOC designs. POWER consumption has become a bottleneck in microprocessor design.
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Structure and Hierarchical Control Method of Battery‐Based Hybrid Power Flow Controller
International Transactions on Electrical Energy Systems, Volume 2026, Issue 1, 2026.This article proposes a battery‐based hybrid power flow controller (B‐HPFC), offering enhanced flexibility for power flow regulation and energy storage. First, the structure of B‐HPFC is given, where the cascaded H‐Bridge (CHB) is integrated with the phase‐shifting transformer (PST). The batteries are connected to the modules of CHB.
Hua Shao +6 more
wiley +1 more source
The DFM Control System Based on PLL
Communications, 2009 A specific structure of control system with double fed machine (DFM) is studied in the paper. The DFM is assumed to be a generator with stator winding connected to the power grid and it produces active and reactive powers.
Andrzej Popenda
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DSOGI-PLL based power control method to mitigate control errors under disturbances of grid connected hybrid renewable power systems [PDF]
, 2018 The control of power converter devices is one of the main research lines in interfaced renewable energy sources, such as solar cells and wind turbines.
Celik, Dogan, Meral, Mehmet Emin
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Data Driven Second Integral Sliding Mode Control for the Digital Phase-Locked Loop
IEEE AccessThe high accuracy and flexibility of the digital phase-locked loop (DPLL) make it a versatile tool with a wide range of applications in modern sensor technology.
Haiqin Liu +4 more
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Adaptive Gain Control Method of a Phase-Locked Loop for GNSS Carrier Signal Tracking
International Journal of Antennas and Propagation, 2018 The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a
Zhibin Luo, Jicheng Ding, Lin Zhao
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, 2006 This paper deals with design and realization of a PLL synthesizer for the microwave X−band. The synthesizer is intended for use as a local oscillator in a K−band downconverter.
Kutin, P., Vagner, P.
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Beilstein Journal of Nanotechnology, 2018 A phase-locked loop (PLL) circuit is the central component of frequency modulation atomic force microscopy (FM-AFM). However, its response speed is often insufficient, and limits the FM-AFM imaging speed.
Kazuki Miyata, Takeshi Fukuma
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Fixed lag smoothers for carrier phase and frequency tracking [PDF]
The application of fixed lag smoothing algorithms are presented for the problem of estimation of the phase and frequency of a sinusoidal carrier received in the presence of process noise and additive observation noise.
Hurd, W. J., Kumar, R.
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Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter
IEEE Access, 2016 The synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications. However, it suffers from a poor performance under unbalanced and distorted grid conditions.
Yunlu Li +4 more
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