Results 81 to 90 of about 4,801,356 (217)
Linearized discrete-time model of higher order charge-pump PLLs [PDF]
European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, 29-31 August, 2011In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs).
Paul F. Curran +5 more
core +1 more source
A phase-locked loop (PLL) circuit is the central component of frequency modulation atomic force microscopy (FM-AFM). However, its response speed is often insufficient, and limits the FM-AFM imaging speed.
Kazuki Miyata, Takeshi Fukuma
doaj +1 more source
Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter
The synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications. However, it suffers from a poor performance under unbalanced and distorted grid conditions.
Yunlu Li +4 more
doaj +1 more source
Design and analysis of high performance low noise oscillators and phase lock loops
The design and implementation of high purity, high speed and power efficient clock generation Integrated Circuits continue to be one the greatest challenges facing IC designers today. In order to address this challenge, this thesis considers the modeling
Ke, Li
core +1 more source
Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm
— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion.
H. Miar- Naimi, M. Zabihi
doaj
This paper proposes an enhanced Type 3 phase-locked loop (ET3-PLL) to improve the frequency estimation performance of the conventional Type 3 synchronous reference frame PLL (SRF-PLL) under harmonic distortion.
Youfeng Zhou +6 more
doaj +1 more source
Dual-loop control of transfer delay based PLL for fast dynamics in single-phase AC power systems
© The Institution of Engineering and Technology 2019. Phase-locked loop (PLL) is commonly utilised for AC power systems to detect phase and frequency.
Lu, Dylan Dah‐Chuan +9 more
core +1 more source
DSP-Based Phase Locked Loop designMethodology for Three Phase Grid Synchronization
In this paper, a review of Phase Locked Loop(PLL) algorithms, is proposed methodology is based on voltagerepresentation in a three coordinates: natural (abc), stationary(αβ) and rotating coordinates (dq), in order to meet the gridsynchronization ...
Lopez Muñoz, Jose Andres +2 more
core +1 more source
In this paper, a sensorless field-oriented vector control (FOC) strategy combining an improved adaptive sliding mode observer (IASMO) and a finite-position-set phase-locked loop (FPS-PLL) is proposed for a surface permanent magnet synchronous motor ...
Xiang Wang +6 more
doaj +1 more source
PLL-based battery charge circuit topology
[[abstract]]In this paper, a phase-locked battery charger (PLBC) is proposed to show that a phase-locked loop (PLL) is a perfect circuit topology for battery charging. The circuit topology of the PLBC is almost the same as that of the PLL and it inherits
Chen, Liang‐Rui
core

