Results 81 to 90 of about 4,801,356 (217)

Linearized discrete-time model of higher order charge-pump PLLs [PDF]

open access: yes, 2011
European Conference on Circuit Theory and Design (ECCTD), Linkoping, Sweden, 29-31 August, 2011In this paper, we derive linearized discrete-time models of higher order Charge-Pump Phase-Locked Loops (CPPLLs).
Paul F. Curran   +5 more
core   +1 more source

Quantitative comparison of wideband low-latency phase-locked loop circuit designs for high-speed frequency modulation atomic force microscopy

open access: yesBeilstein Journal of Nanotechnology, 2018
A phase-locked loop (PLL) circuit is the central component of frequency modulation atomic force microscopy (FM-AFM). However, its response speed is often insufficient, and limits the FM-AFM imaging speed.
Kazuki Miyata, Takeshi Fukuma
doaj   +1 more source

Performance Improvement of Quasi-Type-1 PLL by using a Complex Notch Filter

open access: yesIEEE Access, 2016
The synchronous reference frame phase-locked loop (SRF-PLL) is widely used for synchronization applications. However, it suffers from a poor performance under unbalanced and distorted grid conditions.
Yunlu Li   +4 more
doaj   +1 more source

Design and analysis of high performance low noise oscillators and phase lock loops

open access: yes, 2010
The design and implementation of high purity, high speed and power efficient clock generation Integrated Circuits continue to be one the greatest challenges facing IC designers today. In order to address this challenge, this thesis considers the modeling
Ke, Li
core   +1 more source

Nonlinear optimized Fast Locking PLLs Using Genetic Algorithm

open access: yesIranian Journal of Electrical and Electronic Engineering, 2009
— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion.
H. Miar- Naimi, M. Zabihi
doaj  

An Enhanced Type 3 Phase-Locked Loop with Improved Frequency Estimation Capability Under Grid Distortion

open access: yesEng
This paper proposes an enhanced Type 3 phase-locked loop (ET3-PLL) to improve the frequency estimation performance of the conventional Type 3 synchronous reference frame PLL (SRF-PLL) under harmonic distortion.
Youfeng Zhou   +6 more
doaj   +1 more source

Dual-loop control of transfer delay based PLL for fast dynamics in single-phase AC power systems

open access: yes, 2019
© The Institution of Engineering and Technology 2019. Phase-locked loop (PLL) is commonly utilised for AC power systems to detect phase and frequency.
Lu, Dylan Dah‐Chuan   +9 more
core   +1 more source

DSP-Based Phase Locked Loop designMethodology for Three Phase Grid Synchronization

open access: yes, 2021
In this paper, a review of Phase Locked Loop(PLL) algorithms, is proposed methodology is based on voltagerepresentation in a three coordinates: natural (abc), stationary(αβ) and rotating coordinates (dq), in order to meet the gridsynchronization ...
Lopez Muñoz, Jose Andres   +2 more
core   +1 more source

Sensorless Strategy for Controlling SPMSM Combining Improved Adaptive SMO and Finite-Position-Set PLL

open access: yesActuators
In this paper, a sensorless field-oriented vector control (FOC) strategy combining an improved adaptive sliding mode observer (IASMO) and a finite-position-set phase-locked loop (FPS-PLL) is proposed for a surface permanent magnet synchronous motor ...
Xiang Wang   +6 more
doaj   +1 more source

PLL-based battery charge circuit topology

open access: yes, 2012
[[abstract]]In this paper, a phase-locked battery charger (PLBC) is proposed to show that a phase-locked loop (PLL) is a perfect circuit topology for battery charging. The circuit topology of the PLBC is almost the same as that of the PLL and it inherits
Chen, Liang‐Rui
core  

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