Results 71 to 80 of about 4,801,356 (217)
Phase-locked-loop with reduced clock jitter [PDF]
, 2003 The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are ...
van de Beek, R.C.H. +2 more
core +1 more source
Laser &Photonics Reviews, Volume 20, Issue 14, 22 July 2026.This work demonstrates a high‐fidelity stability transfer from an optical reference to a high‐repetition‐rate microcomb using a mode‐locked laser bridge. By employing electro‐optic sampling timing detection, femtosecond‐level synchronization and 10−18‐level fractional frequency stability are achieved.
Changmin Ahn +4 more
wiley +1 more source
Phase-Locked-Loop With Reduced Clock Jitter [PDF]
, 2005 The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are ...
Vaucher, Cicero S. +2 more
core +1 more source
A fast three-phase synchronization technique with parallel structure
Energy Reports, 2020 For many grid-connected equipment, the phase and frequency of grid voltage are crucial synchronization information. A phase-locked loop (PLL) is usually employed to obtain the information.
Jinbo Li +5 more
doaj +1 more source
Comparative Study of Phase Lead Compensator based In-loop Filtering Method in Single-Phase PLL
, 2020 Accurate estimation of grid voltage parameters (phase, frequency and amplitude) from Phase Locked Loop (PLL) is a challenging task under distorted and abnormal grid conditions.
Golsorkhi, MS +14 more
core +1 more source
Phase-Locked-loop with reduced clock jitter [PDF]
, 2009 The present invention relates to a phase-locked-loop (PLL) circuit and a method for controlling such a PLL circuit, wherein the frequency of an input reference signal and the frequency of a feedback signal derived from an output oscillation signal are ...
Vaucher, Cicero Silveira +2 more
core +1 more source
Data Driven Second Integral Sliding Mode Control for the Digital Phase-Locked Loop
IEEE AccessThe high accuracy and flexibility of the digital phase-locked loop (DPLL) make it a versatile tool with a wide range of applications in modern sensor technology.
Haiqin Liu +4 more
doaj +1 more source
CMOS switched current phase-locked loop [PDF]
, 1997 The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 µm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz.
Leenaerts, D.M.W. +2 more
core +1 more source
Adaptive Gain Control Method of a Phase-Locked Loop for GNSS Carrier Signal Tracking
International Journal of Antennas and Propagation, 2018 The global navigation satellite system (GNSS) has been widely used in both military and civil fields. This study focuses on enhancing the carrier tracking ability of the phase-locked loop (PLL) in GNSS receivers for high-dynamic application. The PLL is a
Zhibin Luo, Jicheng Ding, Lin Zhao
doaj +1 more source
The DFM Control System Based on PLL
Communications, 2009 A specific structure of control system with double fed machine (DFM) is studied in the paper. The DFM is assumed to be a generator with stator winding connected to the power grid and it produces active and reactive powers.
Andrzej Popenda
doaj +1 more source