Results 111 to 120 of about 22,805 (227)

Design and simulation optimization of phase-locked loop structure for phase-shifting power supply

AIP Advances
A phase-locked loop (PLL) of a phase-shifting power supply for the power system is designed in this paper. Taking the industrial frequency current as the reference signal, the input and output characteristics of the phase-frequency detector with charge ...
Qingchan Liu, Tengbin Li, Yao Zhong, Cong Lin, Junlin Zhang, Zhengang Zhao   +5 more
doaj   +1 more source

A Tone-Aided/Dual Vestigial Sideband (TA/DVSB) system for mobile satellite channels [PDF]

Tone-aided modulation is one way of combatting the effects of multipath fading and Doppler frequency shifts. A new tone-aided modulation format for M-ary phase-shift keyed signals (MPSK) is discussed.
Depaolo, Anthony D., Millar, Gilbert M., Saulnier, Gary J.   +2 more
core   +1 more source

PLL Frequency Stability Enhancement Under Weak Grid Considering Reactive Current Support

CES Transactions on Electrical Machines and Systems
The phase-locked loop (PLL) plays an essential role for synchronizing renewable power generation to the grid. However, as per the grid-code compliance for reactive current support, the PLL output frequency fluctuates significantly and exceeds the ...
Bin Hu, Ling Zhan, Heng Nian, Donglian Qi   +3 more
doaj   +1 more source

Impedance-Phase and Magnitude Control Method to Improve Stability of Grid-Connected Inverters in Weak Grid

CSEE Journal of Power and Energy Systems
Grid impedance and phase-locked loop (PLL) are critical factors for the stability of the grid-connected inverters (GCIs) in a weak grid. They are the positive feedback control loops formed by PLL in the GCI with grid impedance.
Chunming Tu, Jiayuan Gao, Fan Xiao, Qi Guo, Fei Jiang   +4 more
doaj   +1 more source

A study of third-order Phase-Locked Loop (PLL) systems

, 2002
In this dissertation, various types of phase-locked loop systems are introduced. It describes the most commonly used third-order PLL systems in the wireless communication environment. It also describes the major drawbacks of the third-order PLLs that exist in the designing of this higher-order system. Master of Science (Consumer Electronics)
openaire   +1 more source

DESIGN OF ALL DIGITAL PHASE LOCKED LOOP (D-PLL) WITH FAST ACQUISITION TIME

International Journal of Research in Engineering and Technology, 2013
A Digital PLL is designed with improved acquisition time and power efficiency. The implemented D-PLL can operate from 6.54MHz to 105MHz with a power dissipation of is 7.763μW (at 210MHz) with 1.2V supply voltage. The D-PLL is synthesized using cadence RTL compiler in 45nm CMOS process technology.
openaire   +1 more source

A Subsampling Phase-Locked Loop with a Dual Charge Pump Based on Capacitor Multipliers for CMOS Image Sensor. [PDF]

Micromachines (Basel)
Lin Y, Wang B, Jin L, Tang Z, Ye F, Xie R, Wu L, Shi G, Liu H.   +8 more
europepmc   +1 more source

An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [PDF]

Sensors (Basel)
Nguyen TVH, Pham CK.
europepmc   +1 more source

A State-Space Framework for Parallelizing Digital Signal Processing in Coherent Optical Receivers. [PDF]

Sensors (Basel)
Wang J, Wang Z, Liu D.
europepmc   +1 more source

Adaptive Modulation Tracking for High-Precision Time-Delay Estimation in Multipath HF Channels. [PDF]

Sensors (Basel)
Ji Q, Wu H.
europepmc   +1 more source