Results 171 to 180 of about 22,805 (227)

On-Line Musical Beat Tracking with Phase-Locked-Loop (PLL) Techniique

2007 Digest of Technical Papers International Conference on Consumer Electronics, 2007
An on-line beat tracking algorithm based on the digital phase-locked-loop (PLL) technique is proposed in this work, which estimates both the music tempo and the position of beat pulses in real time. In addition to a detailed description of the proposed algorithm, we show that the PLL-technique is effective in its tracking performance and simple to ...
Yu Shiu, C.-C. Jay Kuo
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Optimization of Phase-Locked Loop (PLL) System Parameters

2004
The paper investigates the optimization of parameters for digital phase-locked loop (PLL) systems in order to enhance noise immunity. A Gaussian distribution is assumed for phase deviations of input sync pulses. A mathematical model of the PLL is developed, and a quality criterion based on the output phase deviation variance is proposed. Constraints on
Abdullayev, Isa M., Suleymanov, Ilhami A.   +1 more
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Extended analysis of SSN effect on phase-locked loop (PLL) circuit

2009 IEEE Electrical Design of Advanced Packaging & Systems Symposium (EDAPS), 2009
Electronic devices are increasingly susceptible to simultaneous switching noise (SSN) as devices shrink in size and operate at lower voltage to achieve higher speed. This is a major concern in high-speed system designs as SSN causes voltage and timing variations which affect signal integrity.
Joseph Kho, Chooi Ian Loh, Wui Hung Moo, Chee Seong Fong, Man On Wong   +4 more
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Grid Connected Photovoltaic (PV) Inverter with Robust Phase-Locked Loop (PLL)

2006 IEEE/PES Transmission & Distribution Conference and Exposition: Latin America, 2006
An array of solar panels is connected to the mains through a three-phase active voltage-source inverter and a step-up transformer. The inverter synchronizes to the grid by means of a robust phase-locked loop (PLL), using input's quadrate method, and a multi-variable filter removes voltage harmonics caused by unbalance and distortion.
T. Ostrem, W. Sulkowski, L. Norum, C. Wang   +3 more
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Trusted verification test bench development for Phase-Locked Loop (PLL) hardware insertion

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), 2013
Trusted design and verification presents new challenges for the case of using Intellectual Property (IP) in mixed signal systems. A Digitally Controlled Oscillator (DCO) subcomponent of a Phase-Locked Loop (PLL) is utilized as an example through which the presented verification principles may be applied to PLL tests on the Texas Instruments Analog ...
Adam G. Kimura, Kai-Wei Liu, Siddharth Prabhu, Steven B. Bibyk, Greg Creech   +4 more
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Stabilizing Condition of Grid-Connected VSC as Affected by Phase Locked Loop (PLL)

IEEE Transactions on Power Delivery, 2022
The small signal stability of the system that one single VSC is connected to an infinite source via the line is investigated in this letter. An analytical sufficient and necessary stabilizing condition for such system is derived based on the linearized model.
Yujun Li, Zhengchun Du
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Hardware Description Language Phase-Locked Loop (HDL-PLL) Open Architecture for FPGAs

2018 IEEE Nuclear Science Symposium and Medical Imaging Conference Proceedings (NSS/MIC), 2018
This contribution aims to be a proof of the feasibility of a fully open architecture in Hardware Description Language of a Phase-Locked Loop (HDL-PLL) implemented in Field Programmable Gate Array (FPGA).Main parts of the system are the Phase-Frequency Detector (PFD) based on a Time-to-Digital Converter (TDC) and the Digital-Controlled Oscillator (DCO ...
Lusardi, N., Garzetti, F., Gatti, L., Geraci, A.   +3 more
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PLL (Phase Locked Loop)

1992
Eine Phasenregelschleife (PLL, Phase Locked Loop) ist ein Schaltkreis der einem externen Referenzsignal erlaubt, die Frequenz und die Phase eines Oszillators in der Schleife zu steuern. Die Frequenz des Oszillators in der Schleife kann dabei dieselbe wie die Referenzfrequenz sein oder ein Vielfaches davon.
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ASIC clock distribution using a phase locked loop (PLL)

[1991] Proceedings Fourth Annual IEEE International ASIC Conference and Exhibit, 2002
Transferring data between ASIC chips at frequencies above 40 MHz requires special on-chip circuitry in current sub-micron technologies. Phase locked loops can provide clock skew management in ASIC devices to help compensate for clock tree insertion delays and process, temperature and voltage variations allowing maximum multi-chip system performance. >
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Computer simulation and parameter optimization of phase-locked loops (PLL)

SIMULATION, 1971
The automatic control and simulation of phased- locked loops (PLL) is treated with particular em phasis on the use of analog and digital computer simulation techniques. The object is to obtain an adequate mathematical model for the PLL and then to use this model to optimize parameters and investi gate pull-in performance. Results are presented for the
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