Results 181 to 190 of about 22,805 (227)

Phase-Locked Loop (PLL)

2010
PLL is the heart of practically all electronic components and or modules where different clock frequencies are required to synchronize the data transmitting and receiving to and from externals respectively. The input clock to the PLL is much lower than the DSP maximum clock frequency.
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Phase Locked Loop PLL-Based Frequency Synthesizers: A General Overview

2019
This work summarizes the operating features for type II second-order Phase-Locked Loop (PLL)-based Frequency Synthesizers (FS) from the set of equations of linear dynamic modeling for defining the corresponding block level and system level transfer functions and developing the reference design equations for the Low Pass Filter (LPF) components sizing.
R. N. S. Raphael, Agord M. Pinto, Leandro T. Manera, Saulo Finco   +3 more
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Phase-Locked Loop (PLL)-Based Frequency Synthesizer for Digital Systems Driving

2019
This work describes the implementation and operation features for a Phase-Locked Loop (PLL) architecture-based frequency synthesizer for clock generation and digital systems driving. From a programmable structure, considering an input reference frequency FREF = 50 MHz, schematic level simulation results indicate the possibility for generation of 3 ...
R. N. S. Raphael, Agord M. Pinto, Leandro T. Manera, Saulo Finco   +3 more
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Phase Locked Loop (PLL) based self-oscillating controller for LCC resonant converters

4th IET International Conference on Power Electronics, Machines and Drives (PEMD 2008), 2008
The paper describes a controller for the LCC resonant converter that employs a Phase-Locked Loop (PLL) to generate switch timing signals from measurements of current in the resonant circuit. A major advantage of the control methodology is that operation is automatically restricted to be above the resonant frequency thereby ensuring inductive switching.
A.J. Gilbert, M.P. Foster, D.A. Stone, C.M. Bingham   +3 more
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Analysis of lock-loss events in discrete-time phase locked loop (PLL)

Proceedings of the 2004 11th IEEE International Conference on Electronics, Circuits and Systems, 2004. ICECS 2004., 2005
Lock-loss phenomena were studied extensively for continuous-time phase locked loop (PLL), and closed form analytical expressions for the mean time to lose lock (MTLL) has been derived under the assumptions that the input is a phase modulated sine wave, and that the additive noise associated with the input can be added to the detector output.
L. Brecher, N. Sommer, E. Weinstein
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THE EFFECT OF THE FORCING FUNCTION ON DISRUPTION OF A PHASE-LOCKED LOOP (PLL)

International Journal of Bifurcation and Chaos, 2000
In this paper we compare the disruption of a second-order type II phase-locked loop (PLL) by two different waveforms: a sinusoid and a sawtooth. The choice of these two waveforms results from a novel approach to the problem of determining an appropriate forcing function for studying the disruption of such systems.
Booker, S. M., Smith, P. D., Brennan, P., Bullock, R.   +3 more
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Efficient digital techniques for implementing a class of fast phase-locked loops (PLL's)

IEEE Transactions on Industrial Electronics, 1996
Circuit configurations making use of counters are described to efficiently implement controllers for time-optimal and finite-time responses in phase-locked loops (PLLs). The new PLLs, solving the responsiveness problem with conventional PLLs, require quite complicated operations, including adders and subtracters.
F. Kobayashi, M. Haratsu, M. Yabumoto, M. Nakano   +3 more
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Frequency-to-Voltage Converter Based Dual-Loop PLL with Variable Phase Locking Capability

2022
A novel frequency-to-voltage converter (FVC) based phase-locked loop (PLL) is proposed to overcome the inability of an FVC-based frequency-locked loop (FLL) to lock phase. The proposed dual-loop PLL adds variable phase-locking capability, such that the phase locking angle can vary from 0o – 360o.
Z Saifullah, Paul Furth, SriHarsh Pakala, Alejandro Roman-Leora   +3 more
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Fixed reference frame phase-locked loop (FRF-PLL) for unbalanced line voltage conditions

2008 IEEE Power Electronics Specialists Conference, 2008
In this work a phase-locked loop (PLL) is presented, which is able to provide an estimation of the angular frequency, and both the positive and negative sequences of the fundamental component of a three-phase signal. These sequences are provided in fixed reference frame coordinates, and thus the proposed algorithm is referred as fixed reference frame ...
M.F. Martinez-Montejano, G. Escobar, R.E. Torres-Olguin   +2 more
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LQR based PI Controller Tuning for Transport Delay-Phase Locked Loop (TD-PLL)

2018 3rd International Innovative Applications of Computational Intelligence on Power, Energy and Controls with their Impact on Humanity (CIPECH), 2018
A new design procedure for optimal tuning of PI Controller parameter tuning for Transport delay - Phase Locked Loop (TD-PLL) using Linear Quadratic Regulator (LQR) based approach is presented in this paper to ensure optimal control effort. The proposed tuning methodology is also compared with other existing tuning methods under various grid ...
Mohd Afroz Akhtar, Srishti Choudhury, Suman Saha   +2 more
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