Results 31 to 40 of about 16,793 (159)
IEEE AccessSynchronization of single-phase inverters is a challenging task due to the difficulty of deriving a rotating voltage frame, in the absence of adequate information from the other two phases. Moreover, modern standards, such as the fault ride-through (FRT)
Evangelos E. Pompodakis +5 more
doaj +1 more source
A generalized phase resetting method for phase-locked modes prediction. [PDF]
PLoS ONE, 2017 We derived analytically and checked numerically a set of novel conditions for the existence and the stability of phase-locked modes in a biologically relevant master-slave neural network with a dynamic feedback loop.
Sorinel A Oprisan, Dave I Austin
doaj +1 more source
Synthesis of Phase-locked Loop System Structure with Adaptation Based on Combined-maximum Principle
MATEC Web of Conferences, 2016 The synthesis of the structure of the phase-locked loop system is performed based on the generalized power function maximum condition. The system effectiveness in the lock-on mode is studied via numerical simulation.
Kostoglotov Andrey Aleksandrovich +3 more
doaj +1 more source
Transactions on Environment and Electrical Engineering, 2016 Proper synchronization of Distributed Generator with grid and its performance in grid-connected mode relies on fast and precise estimation of phase and amplitude of the fundamental component of grid voltage. However, the accuracy with which the frequency
Kalpeshkumar Rohitbhai Patil +1 more
doaj +1 more source
IEEE Access, 2020 With the rapid development of industrialization, the proportion of electric arc furnaces (EAF) in distribution networks is getting higher and higher. Aiming at the problem that grid voltage is distorted by a large number of arc furnace nonlinear loads ...
Lingguo Kong +4 more
doaj +1 more source
IEEE Access, 2019 The enhanced phase-locked loop (EPLL) adds an amplitude estimate to the conventional phase-locked loop (PLL), which solves the problem of double-frequency disturbance in the Phase-Locked Loop mathematical model at steady state.
Dongyang Sun +4 more
doaj +1 more source
Reference Spur Reduction Techniques for a Phase-Locked Loop
IEEE Access, 2019 This paper presents the reference spur reduction techniques for an analog phase-locked loop (PLL). A simple leakage compensation loop is proposed, which cancels the leakage current of the PLL loop filter with a negligible power overhead.
Han-Gon Ko +3 more
doaj +1 more source
A grid frequency estimation method based on moving average filter half-tangent phase-locked loop
Diance yu yibiaoThis paper proposes a half-tangent phase-locked loop (HTan-PLL) with a moving average filter (MAF) for estimating grid frequency. The proposed PLL utilizes a half-tangent phase detector (PD) and introduces MAF into the phase-locked loop to address ...
WANG Wenguo, ZHANG Ben
doaj +1 more source
مهندسی مخابرات جنوبThis paper comprehensively investigates how the control voltage settles in Voltage Controlled Oscillators (VCO) by considering all non-ideal factors in phase lock loop circuits. Also, the different structures of the phase detector and their effect on the
Reihaneh Nazaraghaei +2 more
doaj
Extending locked range of digital phase-locked loop by prediction estimation of states
Tongxin xuebao, 2008 A method to extend locked range of the positive zero crossing detection digital phase-locked loop（ZC-DPLL） was proposed.The nonlinear dynamical model of phase error of a non-controlled DPLL is firstly built,linearation predic-tion estimation of phase ...
ZHAO Yi-bo1 +3 more
doaj +2 more sources