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AMF-responsive nanobiomagnetite for targeted delivery of amphotericin B against Leishmania amazonensis. [PDF]
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Comparison of PLL-Based and PLL-Less Vector Current Controllers
IEEE Journal of Emerging and Selected Topics in Power Electronics, 2022This paper presents a detailed and rigorous comparison between two vector current control (VCC) approaches for voltage source converters (VSC). A PLL-less VCC (also called the direct power control) has recently been proposed in several major publications with the assumption that it will improve the performance of conventional PLL-based VCC during weak ...
S. Milad Hoseinizadeh +4 more
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Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
Phase-locked loop (PLL) frequency synthesizers are critical building blocks for wireless transceivers. Frequency synthesis requires integrated oscillators and dividers that can provide superior phase noise performance at ultra-high frequencies. This session focuses on design of high-performance PLLs and building blocks, including voltage- and current ...
Fa Foster Dai, Howard C. Luong
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Phase-locked loop (PLL) frequency synthesizers are critical building blocks for wireless transceivers. Frequency synthesis requires integrated oscillators and dividers that can provide superior phase noise performance at ultra-high frequencies. This session focuses on design of high-performance PLLs and building blocks, including voltage- and current ...
Fa Foster Dai, Howard C. Luong
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2003
The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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The function of a PLL is to generate an output clock whose phase is locked to that of the input reference clock. In order to satisfy this condition, the output clock frequency either has to be equal to the input clock frequency or has to be a multiple of the input clock frequency, i.e.
Liang Dai, Ramesh Harjani
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A comparative study between Fractional-N PLL and Flying-Adder PLL
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010Frequency synthesis is one of the most important and most actively researched subjects in the field of VLSI mixed-signal circuit design. Among the existing techniques in this area, Fractional-N architecture is a widely used one for generating frequencies which are not integer multiple of the input reference frequency.
Liming Xiu, Chen-Wei Huang, Ping Gui
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Digital wireline and PLL techniques
2009 IEEE Custom Integrated Circuits Conference, 2009Trends in deeply-scaled CMOS technology motivate designers to carefully consider using more digital circuitry and digital control techniques for high-speed wireline transceivers and related building blocks. This session presents recent developments in the design and analysis of various digital approaches.
Gu-Yeon Wei, Afshin Momtaz
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14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2011
In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible.
Krzysztof Siwiec +2 more
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In this paper PLL Design tool, created in Matlab from MathWorks, has been presented. The tool allows to analyze loop stability and phase noise of PLL, based on phase-locked loop linear model. Fast evaluation of loop filter components values for popular passive and active filters is possible.
Krzysztof Siwiec +2 more
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ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016
This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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This paper compares the properties of traditional digital phase-locked loops based on multi-bit, high-resolution time-to-digital converters and those based on bang-bang phase detectors. Novel analysis is presented which show that bang-bang digital PLLs allow better phase noise and spur performance at lower power consumption, area and complexity.
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PLL system for harmonic analysis
2011 10th International Conference on Environment and Electrical Engineering, 2011PLL principles system and its applications in harmonic analysis are firstly discussed and then integrated presenting methods to increase the PLL-based instrumentation efficiency. A comparison between the performance of systems before and after the application of these methods are shown to validate the efficiency o f the proposed methods.
ANTONELLI A +2 more
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Hybrid PLL architectures and implementations
2018 IEEE Custom Integrated Circuits Conference (CICC), 2018SSCS Webinar ...
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