Results 181 to 190 of about 20,654 (228)

The convergence of a PLL with variable parameters

International Journal of Circuit Theory and Applications, 1990
AbstractA phase‐locked loop with variable parameters is considered. In such a system it is possible to obtain a short convergence time together with a small bandwidth. It is supposed that the PLL's parameters cannot be switched and there is a restriction on the velocity of the parameter variation.An optimal strategy of parameter variation is obtained ...
Dov Wulich, Moshe Bar
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Preparation of PLL-PEG-PLL and its application to DNA encapsulation

Science in China Series B: Chemistry, 2006
PLL-PEG-PLL was synthesized by deprotection of the amino group of PLL(Z)-PEG-PLL(Z). The properties of the polyion complex (PIC) micelles comprising of PLL-PEG-PLL and DNA were investigated. The results showed that the core of PIC was formed by PLL and DNA through electrostatic interactions, and PEG was shell of PIC, so PIC micelles in aqueous medium ...
Zigang Yang, Fen Zhou, Jianjun Yuan, Lixin Ma, Chao Zhai, Shiyuan Cheng   +5 more
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Digital lock detector for PLL

Proceedings of IEEE East-West Design & Test Symposium (EWDTS'08), 2008
The purpose of this work is to add one more circuit into the traditional PLL to define the lock condition. Fully digital lock detector is presented. Presented circuit provides a simple design, process independence and design automation.
Vazgen Melikyan, Aristakes Hovsepyan, Mkrtich Ishkhanyan, Tigran Hakobyan   +3 more
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Cascade three-phase PLL for unbalance and harmonic distortion operation (CSRF-PLL)

IECON 2014 - 40th Annual Conference of the IEEE Industrial Electronics Society, 2014
This paper presents a phase-locked loop (PLL) method aimed to provide an estimation of the phase angle and the amplitude of the fundamental positive sequence component of a three-phase reference signal subject to severe unbalance and high harmonic distortion. In addition the proposed scheme provides the estimation of the angular frequency, and both the
Gerardo Escobar, Carl Ngai Man Ho, Sami Pettersson, Manuel J. Lopez-Sanchez, Andres A. Valdez-Fernandez   +4 more
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An Algorithm for Automatic Tuning of PLLs

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007
In this paper we propose a new method for the automatic tuning of PLLs with switched capacitor banks in their VCOs. The method is implemented on a 7 GHz 130-nm CMOS PLL with 5 binary control bits. Measurement results are provided and analysis of the method is illustrated.
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Equivocation as a Cause of PLL Hangup

IEEE Transactions on Communications, 1982
The role of phase equivocation in hangup of phase-lock loops is clarified. Equivocation can occur and lead to hangup if and only if the phase detector characteristic is discontinuous at the reverse-slope null.
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Dtc-based pll and method for operating the dtc-based pll

2018
The disclosure provides a phase locked loop, PLL, for phase locking an output signal to a reference signal. The PLL comprises a reference path providing the reference signal to a first input of a phase detector, a feedback loop providing the output signal of the PLL as a feedback signal to a second input of the phase detector, a controllable oscillator
Markulic, Nereo, Liu, Yao, Craninckx, Jan   +2 more
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Εφαρμογές PLL:

2009
Στο πρώτο κεφάλαιο γίνεται αναφορά στην έννοια του χάους και σύντομη ιστορική διαδρομή με βάση τους πρώτους θεωρητικούς επιστήμονες που ασχολήθηκαν με αυτό. Στην συνέχεια περιγράφονται τα δυναμικά κυκλώματα και η χαοτική συμπεριφορά των ηλεκτρικών κυκλωμάτων.
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An 8.5–12.5GHz multi-PLL clock architecture with LC PLL and Ring PLL for multi-lane multi-protocol SerDes

2017 International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2017
This paper presents a multi-PLL clock architecture used in a 4-lane multi-protocol serial link applications. The clock architecture consists of one public LC PLL and four standalone ring PLLs placed within each lane. A swtich capacitor array based LC VCO is used in the LC PLL to enlarge the frequency tuning range and decrease the VCO gain.
Yajun He, Ziqiang Wang, Han Liu, Fangxu Lv, Shuai Yuan, Chun Zhang, Xiang Xie, Hanjun Jiang   +7 more
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Observer-Controller Digital PLL

IEEE Transactions on Circuits and Systems I: Regular Papers, 2010
A digital phase-locked loop (DPLL) has been recently developed to exploit the increasing transistor speed of modern process technology. By employing a digitally controlled oscillator (DCO) and a time-to-digital converter (TDC), the loop filter of a DPLL becomes all-digital.
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