Results 281 to 290 of about 179,155 (337)

A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation

IEEE Journal of Solid-State Circuits, 2022
Different from the conventional two-point modulation (TPM) type-II phase-locked loops (PLLs) requiring non-trivial gain calibrations and TPM type-III PLLs with loop stability concern and limited chirp rate, a self-adapting gain mismatch TPM type-II ...
W. Deng, Zipeng Chen, Haikun Jia, Angxiao Yan, Shiyan Sun, Guopei Chen, Zhihua Wang, B. Chi   +7 more
semanticscholar   +1 more source

New Perspectives on Stability of Decoupled Double Synchronous Reference Frame PLL

IEEE transactions on power electronics, 2021
Modeling and interpretation of synchronization stability of energy conversion systems with the unbalanced grid is a very practical, complicated, and less explored topic.
P. D. Achlerkar, B. K. Panigrahi
semanticscholar   +1 more source

Transient Stability Enhancement Control Strategy Based on Improved PLL for Grid Connected VSC during Severe Grid Fault

IEEE transactions on energy conversion, 2021
In this article, the transient synchronization process of the grid-connected voltage source converters (VSC) is studied detailly. Firstly, the phase-locked loop (PLL)-synchronized VSC is modeled according to the rotor motion equation of synchronous ...
Yuan Liu, Jun Yao, Jinxin Pei, Yang Zhao, P. Sun, Deiyin Zeng, Shiyue Chen   +6 more
semanticscholar   +1 more source

Accurate Phase Detection System Using Modified SGDFT-Based PLL for Three-Phase Grid-Interactive Power Converter During Interharmonic Conditions

IEEE Transactions on Instrumentation and Measurement, 2022
Grid synchronization algorithm is used to track the fundamental phase angle and frequency of the grid voltages/ currents accurately, to generate the reference currents for control of grid-interactive power converters.
K. Sridharan, B. Babu
semanticscholar   +1 more source

Influence of PLL on Stability of Interconnected Grid-Forming and Grid-Following Converters

IEEE transactions on power electronics
This letter analyzes the impact of a phase-locked loop (PLL) on small-signal stability in a system of interconnected grid-forming and grid-following (GFL) converters.
Yang Wu, Heng Wu, F. Zhao, Zejie Li, Xiongfei Wang   +4 more
semanticscholar   +1 more source

PLL Position and Speed Observer With Integrated Current Observer for Sensorless PMSM Drives

IEEE transactions on industrial electronics (1982. Print), 2020
In this article, a phase-locked loop (PLL) rotor position and speed observer, including an integrated decoupled stator current observer, is proposed for wide-speed-range sensorless control of permanent magnet synchronous motor (PMSM) drives. This new PLL
C. Lascu, G. Andreescu
semanticscholar   +1 more source

Impedance-Based Analysis and Stability Improvement of DFIG System Within PLL Bandwidth

IEEE transactions on industrial electronics (1982. Print), 2021
In this article, we analyze the negative impact of phase-locked loop (PLL) on the stability of the doubly fed induction generators system. The small-signal disturbance of PLL mainly affects the coordinate transformation of the rotor current and ...
Bin Hu, H. Nian, Meng Li, Yunyang Xu, Yuming Liao, Jun Yang   +5 more
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������������������ ������ �������������� PLL:

2009
This diplomatic work deals with the development the operation and the various types of PLL. The first chapter deals in the beginning with the importance and the growth of PLL The second chapter begins with the structure of PLL and the elements that compose it which are also developed more analytically below while in the basic mathematic relations that ...
openaire   +2 more sources

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction

IEEE Journal of Solid-State Circuits, 2019
An analog fractional- $N$ sampling phase-locked loop (PLL) is presented. It achieves 75-fs rms jitter, integrated from 10 kHz to 10 MHz, and a −249.7-dB figure of merit (FoM) at the fractional- $N$ mode with a 52-MHz reference clock.
Wanghua Wu, Chih-Wei Yao, K. Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, I. S. Lu, S. Son, T. Cho   +10 more
semanticscholar   +1 more source