Results 71 to 80 of about 5,016,217 (299)
Multimode Oxide‐Based Optoelectronic Memtransistor for In‐Sensor Vision Processing
A multimode optoelectronic memtransistor (OEMT) is demonstrated for vision explainable artificial intelligence (VXAI) hardware. By integrating optical sensing, electrical masking, and non‐volatile memory, the device enables key operations required for generating saliency information.
Min Gu Lee +10 more
wiley +1 more source
A variation tolerant data dependent clock gating approach for PSN attenuated low power digital IC
The evolution of semiconductor industry has brought in high current flow across the power rails (‘Vdd’ and ground) of digital integrated circuits (IC) encapsulated by the modern chip packages. This instigates the uncontrollable generation of Power Supply
Pritam Bhattacharjee +2 more
doaj +1 more source
Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing
A Memristive‐Gated Transistor for Time‐Encoded Analog In‐Memory Computing — By exploiting the RC delay of a self‐rectifying interface‐type memristor, nonlinear I–V distortion is structurally bypassed, enabling 3‐bit nonvolatile memory, spike‐timing‐based analog encoding, and hardware‐calibrated reservoir‐computing validation within a unified device ...
Yun‐Seo Shin +7 more
wiley +1 more source
Multiple power-gating domain (multi-VGND) architecture for improved leakage power reduction
Row-based power-gating has recently emerged as a meet-in-the-middle sleep transistor insertion paradigm between cell-level and block-level granularity, in which each layout row defines the unit of gating, and different rows can be clustered and share the
A. Sathanur +4 more
core +2 more sources
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan +4 more
wiley +1 more source
Placement-aware clustering for integrated clock and power gating
Clock-gating and power-gating are the most widely used solutions for reducing dynamic and static power. They can be potentially integrated so that clock-gating conditions can be used to control the power-gating circuitry thus also reducing static power ...
Andrea Calimera +10 more
core +1 more source
Clock gating and power gating are two of the most effective techniques that are applied today for reducing dynamic and leakage power, respectively, in digital CMOS circuits.
Enrico Macii +9 more
core +2 more sources
Open SystemC Simulator with Support for Power Gating Design
Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge.
George Sobral Silveira +3 more
doaj +1 more source
Bio‐Inspired Artificial Ionic Mechanoreceptor
A skin‐inspired artificial mechanoreceptor based on ionic interactions is presented for biomimetic tactile sensing. Pressure‐driven ionic redistribution within microfluidic channels generates a self‐powered electrical signal without external bias. The generated waveform exhibits mechanoreceptor‐like temporal features, including overshoot and undershoot,
Mohammad Akbari +4 more
wiley +1 more source
A hybrid additive manufacturing platform integrates direct droplet writing of metallic composite with VAT photopolymerization to fabricate architected soft magnetic composites. This approach enables microscale patterning of high‐viscosity materials for programmable actuators, adaptive fluidic devices, and switchable adhesives, offering tunable ...
Yeowon Yoon +4 more
wiley +1 more source

