A watchdog processor to detect data and control flow errors [PDF]
, 2003 A watchdog processor for the MOTOROLA M68040 microprocessor is presented. Its main task is to protect from transient faults caused by SEUs the transmission of data between the processor and the system memory, and to ensure a correct instructions' flow ...
Di Natale, Giorgio +7 more
core +1 more source
A C++-embedded Domain-Specific Language for programming the MORA soft processor array [PDF]
, 2010 MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM).
Purohit, S. +7 more
core +1 more source
FANTOM: Fault Tolerant Task-Drop Aware Scheduling for Mixed-Criticality Systems
IEEE Access, 2020 Mixed-Criticality (MC) systems have emerged as an effective solution in various industries, where multiple tasks with various real-time and safety requirements (different levels of criticality) are integrated onto a common hardware platform.
Behnaz Ranjbar +3 more
doaj +1 more source
A scalable ASIP for BP Polar decoding with multiple code lengths
MATEC Web of Conferences, 2018 In this paper, we propose a flexible scalable BP Polar decoding application-specific instruction set processor (PASIP) that supports multiple code lengths (64 to 4096) and any code rates.
Qiao Wan, Liu Dake
doaj +1 more source
Sensors, 2017 For an inductive wireless power transfer (IWPT) system, maintaining a reasonable power transfer efficiency and a stable output power are two most challenging design issues, especially when coil distance varies.
Zhidong Miao, Dake Liu, Chen Gong
doaj +1 more source
Quantization Framework for Fast Spiking Neural Networks
Frontiers in Neuroscience, 2022 Compared with artificial neural networks (ANNs), spiking neural networks (SNNs) offer additional temporal dynamics with the compromise of lower information transmission rates through the use of spikes.
Chen Li, Lei Ma, Lei Ma, Steve Furber
doaj +1 more source
An efficient processor allocation strategy that maintains a high degree of contiguity among processors in 2D mesh connected multicomputers [PDF]
, 2007 Two strategies are used for the allocation of jobs to processors connected by mesh topologies: contiguous allocation and non-contiguous allocation. In non-contiguous allocation, a job request can be split into smaller parts that are allocated to non ...
Ould-Khaoua, M. +7 more
core +1 more source
MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor [PDF]
, 2009 This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low
Purohit, S. +7 more
core +1 more source
Design of Deep Learning VLIW Processor for Image Recognition
Xibei Gongye Daxue Xuebao, 2020 In order to adapt the application demands of high resolution images recognition and efficient processing of localization in aviation and aerospace fields, and to solve the problem of insufficient parallelism in existing researches, an extensible ...
doaj +1 more source
Neuromodulated Synaptic Plasticity on the SpiNNaker Neuromorphic System
Frontiers in Neuroscience, 2018 SpiNNaker is a digital neuromorphic architecture, designed specifically for the low power simulation of large-scale spiking neural networks at speeds close to biological real-time.
Mantas Mikaitis +3 more
doaj +1 more source