Results 71 to 80 of about 255,822 (257)
A multi-node-upset-resilient 14T SRAM with high read stability for space applications
This paper proposes a voltage-booster read-decoupled radiation-hardened 14T (BDRH14T) SRAM cell. In harsh environments such as space, radiation can flip the stored data in memory cells, resulting in soft errors, including single-event upset (SEU) and ...
Sung-Jun Lim, Sung-Hun Jo
doaj +1 more source
From Shear to Sound: Mechanics–Acoustics Mapping of TPMS Lattices
Triply periodic minimal surface (TPMS) lattices are mapped across mechanical and acoustic performance, revealing that descriptors validated in compression fail under shear. First‐time comparison with trusses included. A transition from porous to resonance‐driven absorption emerges at 25% density.
Lucía Doyle +3 more
wiley +1 more source
A reconfigurable logic‐in‐memory cell composed of triple‐gated feedback field‐effect transistors implements multiple combinational logic functions within a single configuration. By utilizing program gates as dynamic input terminals, the proposed cell performs full adder, full subtractor, 2‐to‐1 multiplexer, and 4‐to‐2 encoder operations without ...
Minhyeok Seol +5 more
wiley +1 more source
Radiation-Hardened 20T SRAM with Read and Write Optimization for Space Applications
With continued CMOS scaling, transistor miniaturization has significantly raised SRAM integration density while lowering the critical charge (Qc), increasing cell vulnerability to spaceborne high-energy particles.
Kon-Woo Kim, Eun Gyo Jeong, Sung-Hun Jo
doaj +1 more source
Grain boundary triple junctions are an essential ingredient of the microstructure of polycrystalline materials. In this study, a triple junction is observed using atomic‐resolution scanning transmission electron microscopy and characterized. Computer simulations reveal that the junction has a dislocation character that is determined by the joining ...
Tobias Brink +4 more
wiley +1 more source
An all‐in‐one analog AI accelerator is presented, enabling on‐chip training, weight retention, and long‐term inference acceleration. It leverages a BEOL‐integrated CMO/HfOx ReRAM array with low‐voltage operation (<1.5 V), multi‐bit capability over 32 states, low programming noise (10 nS), and near‐ideal weight transfer.
Donato Francesco Falcone +11 more
wiley +1 more source
Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell
The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon-based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. JLTFET-based SRAM circuit is designed using the look up table-based Verilog
Aishwarya K, Lakshmi B
doaj +1 more source
Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu +17 more
wiley +1 more source
Ferroelectric tunnel junction devices based on epitaxial undoped ferroelectric HfO2 films demonstrate stable switching endurance of over 106 switching cycles, low write voltages of ±3 V, 16 measured resistance states, and neuromorphic capability.
Markus Hellenbrand +13 more
wiley +1 more source
This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS) technique has recently become an important technology for high-gain ...
Shoji Kawahito, Min-Woong Seo
doaj +1 more source

