Results 261 to 270 of about 12,303 (301)

Trends in reconfigurable logic and reconfigurable computing

9th International Conference on Electronics, Circuits and Systems, 2003
The paper gives a survey on reconfigurable logic and reconfigurable computing technologies, and on recent R&D trends in these areas. The paper also points out the weaker aspects of recent developments and proposes new directions to follow, driven by technology progress, a growing variety of reconfigurable platforms, and, innovations in EDA.
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Reconfigurable computing at Xilinx

Proceedings Euromicro Symposium on Digital Systems Design, 2002
Summary form only givem, as follows. In the last decade and a half, Field Programmable Gate Arrays (FPGAs) have grown from simple devices with a few hundred programmable logic gates to densities beyond one million gates. This growth in density has led to an ever-expanding area of application for these devices.
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Synthesis of efficiently reconfigurable datapaths for reconfigurable computing

2008 International Conference on Field-Programmable Technology, 2008
We present new approach to optimize circuits for dynamic reconfiguration in FPGAs. Within a high level synthesis tool we optimize the binding of operations to resources to achieve high re-use of resources and interconnect between different configurations.
Markus Rullmann, Renate Merker
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Reconfigurable Computing in Ubiquitous Computers: A Roadmap

Sixth International Conference on Parallel and Distributed Computing Applications and Technologies (PDCAT'05), 2005
Reconfigurable Computing (RC) is the presence of hardware that can be reconfigured to implement specific functionality more suitable for specially tailored hardware than on a simple uniprocessor [1]. Although the concept was first proposed in the 1960s, RC has only recently become increasingly popular due to the prevalence of ubiquitous computing: the ...
Lu Yan, Zheng Liang
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A Provable Algorithm for Reconfiguration in Embedded Reconfigurable Computing

29th Annual IEEE/NASA Software Engineering Workshop, 2006
Dynamically reconfigurable computing within embedded computer-based systems can be partially modified at runtime without stopping the operation of the whole system. In this paper, a provable algorithm for runtime evolution of a logical configuration is formally represented by the appropriate graph transformation.
Phan Cong Vinh, Jonathan P. Bowen
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Proteus: a reconfigurable computational network for computer vision

Proceedings., 11th IAPR International Conference on Pattern Recognition. Vol. IV. Conference D: Architectures for Vision and Pattern Recognition,, 1995
The Proteus architecture is a highly parallel, multiple instruction, multiple data machine (MIMD) optimized for large granularity tasks such as machine vision and image processing. The system can achieve 20 gigaflops (80 gigaflops peak). It accepts data via multiple serial links at a rate of up to 640 MB/S.
Robert M. Haralick, Arun K. Somani, Craig M. Wittenbrink, Robert Johnson, Kenneth Cooper, Linda G. Shapiro, Ihsin T. Phillips, Jenq-Neng Hwang, William Cheung, Yung Hsi Yao, Chung-Ho Chen, Larry Yang, Brian Daugherty, Bob Lorbeski, Kent Loving, Tom Miller, Larye Parkins, Steve Soos   +17 more
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Toolset for nano-reconfigurable computing

Microelectronics Journal, 2009
Contrasting with the extensive research focusing on nano-devices properties and fabrication, not enough attention is probably given to computing architectures for these devices. This paper describes a method for mapping an FPGA architecture to a nano-device called NASIC (for Nano-ASIC). This mapping is an illustration of the interest of nano- and micro-
Loïc Lagadec, Bernard Pottier, Damien Picard   +2 more
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Reconfigurable computers

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 2005
Reconfigurable Computers are parallel systems that are designed around multiple general-purpose processors and multiple field programmable gate array (FPGA) chips. These systems can leverage the synergism between conventional processors and FPGAs to provide low-level hardware functionality at the same level of programmability as general-purpose ...
Tarek A. El-Ghazawi, Kris Gaj, Nikitas A. Alexandridis, Allen Michalski, Osman Devrim Fidanci, Mohamed Taher, Esam El-Araby, Esmail Chitalwala, Proshanta Saha   +8 more
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Programming paradigms for reconfigurable computing

Microprocessors and Microsystems, 2005
Abstract High-level programming paradigms are examined to determine their appropriateness for describing systems, which are amenable to automated compilation onto a reconfigurable computing platform. We aim to find a set of language features to act as a basis for future language development which: provide a concise description of the system to be ...
Gareth Lee, George J. Milne
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MORPHEUS: Heterogeneous Reconfigurable Computing

2007 International Conference on Field Programmable Logic and Applications, 2007
Reconfigurable architectures and NoC (network-on-chip) communication systems have introduced new research directions for technology and flexibility issues, which have been largely investigated in the last decades. Exploiting the flexibility of reconfigurable architectures, the run-time adap-tivity through run-time reconfiguration, opens a new area of ...
Florian Thoma, Matthias Kühnle, Philippe Bonnot 0001, Elena Moscu Panainte, Koen Bertels, Sebastian Goller, Axel Schneider, Stéphane Guyetant, Eberhard Schüler, Klaus D. Müller-Glaser, Jürgen Becker 0001   +10 more
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