Results 21 to 30 of about 4,400 (253)
A Hardware Filesystem Implementation with Multidisk Support
International Journal of Reconfigurable Computing, 2009 Modern High-End Computing systems frequently include FPGAs as compute accelerators. These programmable logic devices now support disk controller IP cores which offer the ability to introduce new, innovative functionalities that, previously, were not ...
Ashwin A. Mendon +2 more
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Exploring Graphics Processing Unit (GPU) Resource Sharing Efficiency for High Performance Computing
Computers, 2013 The increasing incorporation of Graphics Processing Units (GPUs) as accelerators has been one of the forefront High Performance Computing (HPC) trends and provides unprecedented performance; however, the prevalent adoption of the Single-Program Multiple ...
Teng Li +2 more
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Reconfigurable cellular computers
Information and Control, 1981 When a collection of processors P1,,Pn< operates in parallel, it is desirable that at any given stage of the computation, each {ifPi should have a task of about the same size to perform, and each {ifPi should require about the same amount of information from the other P's in order to perform its task.
Azriel Rosenfeld, Angela Y. Wu
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Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs
International Journal of Reconfigurable Computing, 2015 Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications.
Gongyu Wang +3 more
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Reduced-Precision Redundancy on FPGAs
International Journal of Reconfigurable Computing, 2011 Reduced-precision redundancy (RPR) has been shown to be a viable alternative to triple modular redundancy (TMR) for digital circuits. This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve ...
Brian Pratt +2 more
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Analysis and Design of a Context Adaptable SAD/MSE Architecture
International Journal of Reconfigurable Computing, 2009 Design of flexible multimedia accelerators that can cater to multiple algorithms is being aggressively pursued in the media processors community. Such an approach is justified in the era of sub-45 nm technology where an increasingly dominating leakage ...
Arvind Sudarsanam +2 more
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Frontiers in Neuroinformatics, 2018 The Si elegans platform targets the complete virtualization of the nematode Caenorhabditis elegans, and its environment. This paper presents a suite of unified web-based Graphical User Interfaces (GUIs) as the main user interaction point, and discusses ...
Gorka Epelde +10 more
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International Journal of Reconfigurable Computing, 2012 As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high ...
Andrew G. Schmidt +3 more
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Secure Boot for Reconfigurable Architectures
Cryptography, 2020 Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry.
Ali Shuja Siddiqui +2 more
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Redsharc: A Programming Model and On-Chip Network for Multi-Core Systems on a Programmable Chip
International Journal of Reconfigurable Computing, 2012 The reconfigurable data-stream hardware software architecture (Redsharc) is a programming model and network-on-a-chip solution designed to scale to meet the performance needs of multi-core Systems on a programmable chip (MCSoPC).
William V. Kritikos +4 more
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