Results 21 to 30 of about 59,938 (276)
Exploring Graphics Processing Unit (GPU) Resource Sharing Efficiency for High Performance Computing
Computers, 2013 The increasing incorporation of Graphics Processing Units (GPUs) as accelerators has been one of the forefront High Performance Computing (HPC) trends and provides unprecedented performance; however, the prevalent adoption of the Single-Program Multiple ...
Teng Li +2 more
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Core-Level Modeling and Frequency Prediction for DSP Applications on FPGAs
International Journal of Reconfigurable Computing, 2015 Field-programmable gate arrays (FPGAs) provide a promising technology that can improve performance of many high-performance computing and embedded applications.
Gongyu Wang +3 more
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Throughput analysis for a high-performance FPGA-accelerated real-time search application [PDF]
, 2012 We propose an FPGA design for the relevancy computation part of a high-throughput real-time search application. The application matches terms in a stream of documents against a static profile, held in off-chip memory.
Chalamalasetti, S.R. +2 more
core +3 more sources
Reduced-Precision Redundancy on FPGAs
International Journal of Reconfigurable Computing, 2011 Reduced-precision redundancy (RPR) has been shown to be a viable alternative to triple modular redundancy (TMR) for digital circuits. This paper builds on previous research by offering a detailed analysis of the implementation of RPR on FPGAs to improve ...
Brian Pratt +2 more
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MORA - an architecture and programming model for a resource efficient coarse grained reconfigurable processor [PDF]
, 2009 This paper presents an architecture and implementation details for MORA, a novel coarse grained reconfigurable processor for accelerating media processing applications. The MORA architecture involves a 2-D array of several such processors, to deliver low
Chalamalasetti, S.R. +3 more
core +1 more source
Analysis and Design of a Context Adaptable SAD/MSE Architecture
International Journal of Reconfigurable Computing, 2009 Design of flexible multimedia accelerators that can cater to multiple algorithms is being aggressively pursued in the media processors community. Such an approach is justified in the era of sub-45 nm technology where an increasingly dominating leakage ...
Arvind Sudarsanam +2 more
doaj +1 more source
Frontiers in Neuroinformatics, 2018 The Si elegans platform targets the complete virtualization of the nematode Caenorhabditis elegans, and its environment. This paper presents a suite of unified web-based Graphical User Interfaces (GUIs) as the main user interaction point, and discusses ...
Gorka Epelde +10 more
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Computational reconfigurable imaging spectrometer
Optics Express, 2017 We demonstrate a novel hyperspectral imaging spectrometer based on computational imaging that enables sensitive measurements from smaller, noisier, and less-expensive components (e.g. uncooled microbolometers), making it useful for applications such as small space and air platforms with strict size, weight, and power requirements.
R M, Sullenberger +4 more
openaire +2 more sources
International Journal of Reconfigurable Computing, 2012 As the number of cores per discrete integrated circuit (IC) device grows, the importance of the network on chip (NoC) increases. However, the body of research in this area has focused on discrete IC devices alone which may or may not serve the high ...
Andrew G. Schmidt +3 more
doaj +1 more source
Reconfigurable Computing for Tool-Path Computation
The International Journal of Advanced Manufacturing Technology, 2003 Tool path generation is one of the most complex problems in Computer Aided Manufacturing. Although some efficient strategies have been developed to solve it, most of them are only useful for 3 and 5 axis standard machining. The algorithm called Virtual Digitising computes the tool path by means of a “virtually digitised” model of the surface and a ...
Jimeno Morenilla, Antonio +1 more
openaire +2 more sources