Results 1 to 10 of about 178,264 (269)
Design of a Four-stage Pipelined Reduced Instruction Set Computing Microprocessor
SSRN Electronic Journal, 2020 This work presents the design of a reduced instruction set computing (RISC) microprocessor in a four-stage pipeline architecture. The nuts and bolts of each block including timing diagrams are elaborated. To be more specific, a hardware solution to pipeline hazards is proposed and verified, i.e. provided the current result of the arithmetic logic unit (
Jinfeng Li
openalex +4 more sources
Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor [PDF]
IEEE Transactions on Reliability, 2014 With the scaling of complementary metal-oxide-semiconductor (CMOS) technology to the submicron range, designers have to deal with a growing number and variety of fault types. In this way, intermittent faults are gaining importance in modern very large scale integration (VLSI) circuits. The presence of these faults is increasing due to the complexity of
Joaquín Gracia-Morán +4 more
openalex +4 more sources
Fast Implementation of High Power Operation in SM9 [PDF]
Jisuanji gongcheng, 2023 The SM9 algorithm is an identification cipher algorithm based on bilinear pairs. The operation process requires multiple higher power operations of twelve domain expansions, and its computing performance is crucial to the application of the SM9 algorithm
Jiangtao WANG, Rong FAN, Zhe HUANG
doaj +1 more source
Rendimiento para la interoperabilidad entre Rasperry pi, ESP8266 y PLC con Node-RED para el IIoT
Ingenius: Revista de Ciencia y Tecnología, 2023 Este trabajo evalúa la viabilidad de integrar en una red descentralizada las placas de bajo costo Raspberry pi, microcontroladores ESP8266 con equipos industriales de Controladores Lógicos Programables (PLC).
J. Torres Ventura +2 more
doaj +1 more source
Quantum compiling with a variational instruction set for accurate and fast quantum computing
Physical Review Research, 2023 The quantum instruction set (QIS) is defined as the quantum gates that are physically realizable by controlling the qubits in quantum hardware. Compiling quantum circuits into the product of the gates in a properly defined QIS is a fundamental step in ...
Ying Lu +3 more
doaj +1 more source
Introducing KeyRing self‐timed microarchitecture and timing‐driven design flow
IET Computers & Digital Techniques, 2021 A self‐timed microarchitecture called KeyRing is presented, and a method for implementing KeyRing circuits compatible with a timing‐driven electronic design automation (EDA) flow is discussed.
Mickael Fiorentino +2 more
doaj +1 more source
RISQ - reduced instruction set quantum computers [PDF]
Journal of Modern Optics, 2000 11 pages, talk given at Fundamentals of Modern Optics V, to appear in Journal of Modern ...
Molmer, Klaus, Sorensen, Anders
openaire +2 more sources
RISC Conversions for LNS Arithmetic in Embedded Systems
Mathematics, 2020 The paper presents an original methodology for the implementation of the Logarithmic Number System (LNS) arithmetic, which uses Reduced Instruction Set Computing (RISC).
Peter Drahoš +4 more
doaj +1 more source
Studia Geotechnica et Mechanica, 2023 In this study, a modification of resonant column/torsional shearing (RC/TS) apparatus was proposed to perform a qualitative analysis of a noncohesive soil specimen vibration during RC tests.
Bujko Marcin +3 more
doaj +1 more source
ED25519: A New Secure Compatible Elliptic Curve for Mobile Wireless Network Security
Jordanian Journal of Computers and Information Technology, 2022 Wireless Sensor Networks (WSNs) create various security threats such as application variance in different sectors along with the model of cryptographic primitive and necessity.
MAUSAM DAS, Zenghui Wang
doaj +1 more source