Results 11 to 20 of about 60,987 (263)

NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor

Sensors, 2020
A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS ...
Tomasz Borejko, Krzysztof Marcinek, Krzysztof Siwiec, Paweł Narczyk, Adam Borkowski, Igor Butryn, Arkadiusz Łuczyk, Daniel Pietroń, Maciej Plasota, Szymon Reszewicz, Łukasz Wiechowski, Witold A. Pleskacz   +11 more
doaj   +1 more source

Reduced Instruction Set Computer (RISC): A Survey

Journal of Physics: Conference Series, 2021
Abstract Today’s modern machines are designed to process real time problems and to do so designers try to make them more performance efficient but while doing this, the complexity of design also increases. So, to maintain a balance between both we have to manage this complexity. Now, a question arises how can we do this?
Harsh, Malti Bansal
openaire   +2 more sources

A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm

Journal of Low Power Electronics and Applications, 2019
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power ...
Jean-Frédéric Christmann, Florent Berthier, David Coriat, Ivan Miro-Panades, Eric Guthmuller, Sébastien Thuries, Yvain Thonnart, Adam Makosiej, Olivier Debicki, Frédéric Heitzmann, Alexandre Valentian, Pascal Vivet, Edith Beigné   +12 more
doaj   +1 more source

An Instruction-Driven Batch-Based High-Performance Resource-Efficient LSTM Accelerator on FPGA

Electronics, 2023
In recent years, long short-term memory (LSTM) has been used in many speech recognition tasks, due to its excellent performance. Due to a large amount of calculation and complex data dependencies of LSTM, it is often not so efficient to deploy on the ...
Ning Mao, Haigang Yang, Zhihong Huang
semanticscholar   +1 more source

Instruction Set Architectures for Quantum Processing Units [PDF]

ISC Workshops, 2017
Progress in quantum computing hardware raises questions about how these devices can be controlled, programmed, and integrated with existing computational workflows.
Keith A. Britt, T. Humble
semanticscholar   +1 more source

Design and Implementation of an IoT-Oriented Energy Management System Based on Non-Intrusive and Self-Organizing Neuro-Fuzzy Classification as an Electrical Energy Audit in Smart Homes

Applied Sciences, 2018
Smart cities are built to help people address issues like air pollution, traffic optimization, and energy efficiency. Electrical energy efficiency has become a central research issue in the energy field.
Yu-Hsiu Lin
doaj   +1 more source

Application of regional meteorology and air quality models based on the microprocessor without interlocked piped stages (MIPS) and LoongArch CPU platforms [PDF]

Geoscientific Model Development
The microprocessor without interlocked piped stages (MIPS) and LoongArch are reduced instruction set computing (RISC) processor architectures, which have advantages in terms of energy consumption and efficiency.
Z. Bai, Z. Bai, Q. Wu, Q. Wu, K. Cao, K. Cao, Y. Sun, H. Cheng, H. Cheng   +8 more
doaj   +1 more source

TCX: A RISC Style Tensor Computing Extension and a Programmable Tensor Processor

ACM Transactions on Embedded Computing Systems, 2022
Neural network processors and accelerators are domain-specific architectures deployed to solve the high computational requirements of deep learning algorithms. This article proposes a new instruction set extension for tensor computing, TCX, using Reduced
Tailin Liang, Lei Wang, Shaobo Shi, J. Glossner, Xiaotong Zhang   +4 more
semanticscholar   +1 more source

Evaluation of CFD Computing Performance on Multi-Core Processors for Flow Simulations

Journal of Advanced Research in Applied Sciences and Engineering Technology, 2022
Previous parallel computing implementations for Computational Fluid Dynamics (CFD) focused extensively on Complex Instruction Set Computer (CISC). Parallel programming was incorporated into the previous generation of the Raspberry Pi Reduced Instruction ...
Iman Fitri Ismail, A. Mohammed, B. Basuno, Siti Aisyah Alimuddin, Mustafa Alas   +4 more
semanticscholar   +1 more source

A system on chip-based real-time tracking system for amphibious spherical robots

International Journal of Advanced Robotic Systems, 2017
Aiming at vision applications of our amphibious spherical robot, a real-time detection and tracking system adopting Gaussian background model and compressive tracking algorithm was designed and implemented in this article.
Shuxiang Guo, Shaowu Pan, Xiaoqiong Li, Liwei Shi, Pengyi Zhang, Ping Guo, Yanlin He   +6 more
doaj   +1 more source