Results 11 to 20 of about 178,264 (269)
Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer
IEEE Micro, 1987 GaAs now allows up to 30K transistors per chip. With such a limitation, can you build a 32-bit CISC on a single GaAs chip? Yes, if you build a reduced instruction set computer and emulate the 32-bit CISC on it.
McNeley, K. J., Milutinovic', V. M.
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Reduced Instruction Set Computer (RISC): A Survey
Journal of Physics: Conference Series, 2021 Abstract Today’s modern machines are designed to process real time problems and to do so designers try to make them more performance efficient but while doing this, the complexity of design also increases. So, to maintain a balance between both we have to manage this complexity. Now, a question arises how can we do this?
Malti Bansal, null Harsh
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A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
Journal of Low Power Electronics and Applications, 2019 Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power ...
Jean-Frédéric Christmann +12 more
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NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor
Sensors, 2020 A dual-frequency all-in-one Global Navigation Satellite System (GNSS) receiver with a multi-core 32-bit RISC (reduced instruction set computing) application processor was integrated and manufactured as a System-on-Chip (SoC) in a 110 nm CMOS ...
Tomasz Borejko +11 more
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Exploration and exploitation in the presence of network externalities [PDF]
, 2003 This paper examines the conditions under which exploration of a new, incompatible technologyis conducive to firm growth in the presence of network externalities.
Arthur W. B. +25 more
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A unified modulo scheduling and register allocation technique for clustered processors [PDF]
, 2001 This work presents a modulo scheduling framework for clustered ILP processors that integrates the cluster assignment, instruction scheduling and register allocation steps in a single phase.
Codina Viñas, Josep M. +2 more
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Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review [PDF]
, 2009 The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range.
Gujarathi, Hemal S +2 more
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Applied Sciences, 2018 Smart cities are built to help people address issues like air pollution, traffic optimization, and energy efficiency. Electrical energy efficiency has become a central research issue in the energy field.
Yu-Hsiu Lin
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A fine-grain time-sharing Time Warp system [PDF]
, 2017 Although Parallel Discrete Event Simulation (PDES) platforms relying on the Time Warp (optimistic) synchronization protocol already allow for exploiting parallelism, several techniques have been proposed to further favor performance.
Pellegrini, Alessandro +1 more
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An Arnoldi-frontal approach for the stability analysis of flows in a collapsible channel [PDF]
, 2016 In this paper, we present a new approach based on a combination of the Arnoldi and frontal methods for solving large sparse asymmetric and generalized complex eigenvalue problems.
Cai, Zongxi +3 more
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