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Reduced Instruction Set Computer [PDF]

, 1992
Seit der Entwicklung der ersten digitalen Rechner wuchs der Umfang und die Komplexitat der Befehlssatze stetig an. So hatte 1948 der MARK I nur sieben Maschinenbefehle geringer Komplexitat wie z.B. Additions- und Sprungbefehle. Nachfolgende Prozessorarchitekturen versuchten, die semantische Lucke (semantic Gap) zwischen hoheren, problemorientierten ...
Wolfram Schiffmann, Robert Schmitz
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A Systolic Neural CPU Processor Combining Deep Learning and General-Purpose Computing With Enhanced Data Locality and End-to-End Performance

IEEE Journal of Solid-State Circuits, 2023
While neural network (NN) accelerators are being significantly developed in recent years, CPU is still essential for data management and pre-/post-processing of accelerators in a commonly used heterogeneous architecture, which usually contains an NN ...
Yuhao Ju, Jie Gu
semanticscholar   +1 more source

P4 and NetFPGA-Based Secure In-Network Computing Architecture for AI-Enabled Industrial Internet of Things

IEEE Internet of Things Journal, 2023
This article proposes a secure in-network computing system based on a simple reduced instruction set architecture, which can be used for processing artificial intelligence and machine learning models in network devices, in an AI-based Industrial Internet
G. Sankaran, K. Sivalingam, Harsh Gondaliya   +2 more
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The Potential of RISC-V Platform in Financial Computing on Option Pricing and Energy Efficiency

IEEE International Conference on Systems, Man and Cybernetics, 2023
The fifth version of the Reduced Instruction Set Computer (RISC-V) is a popular instruction set architecture (ISA) featured for low energy consumption.
Guoxiang Guo, Y. Qi, Minhao Zhu, Yang Wang, Jerome Yen   +4 more
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An Instruction-configurable Post-quantum Cryptographic Processor towards NTRU

Asian Hardware-Oriented Security and Trust Symposium, 2022
Post-quantum cryptography (PQC) is proposed to resist the attack of quantum computer. Among various PQC schemes, lattice-based cryptography depended on learning with errors (LWE) problem has attracted much attention.
Shuo Yang, Dongsheng Liu, Ang Hu, Aobo Li, Jiaming Zhang, Xiang Li, Jiahao Lu, Changwen Mo   +7 more
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URISC: The Ultimate Reduced Instruction Set Computer

International Journal of Electrical Engineering & Education, 1988
URISC is a single-instruction universal computer which appears to be ideal for introducing basic computer organization concepts to novice students. In this paper, the specifications of URISC are given and complete implementations of its control unit are presented.
Farhad Mavaddat, Behrooz Parhami
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RISC-(reduced instruction set computers) [PDF]

IEEE Potentials, 1991
The RISC approach to computer design is described. The use of pipelining, a characteristic feature of RISC computers, is discussed. The simple instruction encoding, memory instructions, and optimizing compilers are examined. Implementation, performance, potential disadvantages, and future trends are considered. >
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RISCing (reduced instruction set computing) the future on hardware.

Healthcare informatics : the business magazine for information and communication systems, 1994
R Cascio
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Reduced instruction set computers

Communications of the ACM, 1985
Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.
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The research and development of reduced instruction set computer

2011 IEEE 3rd International Conference on Communication Software and Networks, 2011
This paper proposed a unified model of computer architecture, data flow-based calculation and structure that flow calculation based on the architecture of a unified calculation of instruction stream-based architecture up CISC and RISC system system that based on the Von Neumann architecture • modern computer system problems and research priorities, and
Yanling Zhou, Xianping Zheng, Ya Liu, Wangping Xiong   +3 more
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