Results 201 to 210 of about 178,264 (269)

An novel cloud task scheduling framework using hierarchical deep reinforcement learning for cloud computing. [PDF]

PLoS One
Cui D, Peng Z, Li K, Li Q, He J, Deng X.
europepmc   +1 more source

Development of an AI-powered AR glasses system for real-time first aid guidance in emergency situations. [PDF]

BioData Min
Abo-Zahhad M, Zakaria MN, Sharaf FM, Ismaiel MM, Hafrag H, Amer YM.   +5 more
europepmc   +1 more source

Reliable computing with ultra-reduced instruction set co-processors

IEEE Micro, 2012
This work presents a method to reliably perform computations in the presence of both hard faults arising from aggressive technology scaling and design defects from human error. The method is based on the observation that a single Turing-complete instruction can mirror any other instruction's semantics.
Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh Tripunitara, Siddharth Garg   +4 more
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Reliable Computing with Ultra-Reduced Instruction Set Coprocessors

Proceedings of the 49th Annual Design Automation Conference, 2014
This work presents a method to reliably perform computations in the presence of hard faults arising from aggressive technology scaling, and design defects from human error. Our method is based on an observation that a single Turing-complete instruction can mirror the semantics of any other instruction.
Dan Wang, Aravindkumar Rajendiran, Sundaram Ananthanarayanan, Hiren Patel, Mahesh Tripunitara, Siddharth Garg   +5 more
openalex   +2 more sources

Hewlett-Packard precision architecture: A practical example of reduced instruction set computing

The Physics Teacher, 1987
James T. Hunt
openalex   +2 more sources

RISCing (reduced instruction set computing) the future on hardware.

Healthcare informatics : the business magazine for information and communication systems, 1994
R Cascio
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Reduced Instruction Set Computer Design on FPGA

2021 IEEE 1st International Maghreb Meeting of the Conference on Sciences and Techniques of Automatic Control and Computer Engineering MI-STA, 2021
The main purpose of this paper is to design, verify and implement 16_bit RISC (Reduced Instruction Set Computer) processor that can be used for many embedded applications. The basic modules of this processor are programmed and simulated using Verilog HDL (Hardware Description Language), and implemented on Cyclone IV FPGA (Field Programmable Gate Arrays)
Mohamed M. Eljhani, Veton Z. Kepuska
openaire   +1 more source

Reduced instruction set computers

Communications of the ACM, 1985
Reduced instruction set computers aim for both simplicity in hardware and synergy between architectures and compilers. Optimizing compilers are used to compile programming languages down to instructions that are as unencumbered as microinstructions in a large virtual address space, and to make the instruction cycle time as fast as possible.
openaire   +1 more source

Complex versus reduced instruction set computers

1983 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1983
Recently, considerable controversy has arisen on the use of Reduced Instruction Set Computers (RISCs), when performing general purpose computing tasks. Beyond being the subject of an architecture debate, the concept of reduced instruction sets may have dramatic implications for VLSI design tradeoffs: design time, design methodology, performance and ...
D. Patterson, S. Seccombe
openaire   +1 more source

URISC: The Ultimate Reduced Instruction Set Computer

International Journal of Electrical Engineering & Education, 1988
URISC is a single-instruction universal computer which appears to be ideal for introducing basic computer organization concepts to novice students. In this paper, the specifications of URISC are given and complete implementations of its control unit are presented.
Farhad Mavaddat, Behrooz Parhami
openaire   +1 more source