Results 231 to 240 of about 179,330 (266)

F-RISC/I: fast reduced instruction set computer with GaAs (H) MESFET implementation

[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
F-RISC/I is a monolithic GaAs microprocessor with a seven stage pipeline implemented with SBFL standard cells. It is targeted at a clock rate of 400 MHz with a CPI of 1.45. The impacts of GaAs technology on system architecture, CPU architecture, circuit level optimization, implementation, performance, and testing of F-RISC/I are discussed.
C.K. Tien, C.C. Poon, H. Greub, J.F. McDonald   +3 more
openaire   +1 more source

Reduced-Instruction-Set, Writable-Instruction-Set and Very-Long-Instruction-Word Computers

1991
Instruction sets and their addressing modes and functional classes may grow to be quite complicated. For example, the widely used minicomputer VAX 11/780 has 16 addressing modes and more than 300 unique instructions! Even microprocessors often have complicated instruction sets. The Motorola 68020 recognizes seven data types, employs 18 addressing modes,
openaire   +1 more source

Ada on reduced instruction set computers, for real-time embedded systems

9th IEEE/AIAA/NASA Conference on Digital Avionics Systems, 2002
The 32-bit reduced-instruction-set-computer (RISC)-based processors have been identified by the Joint Integrated Avionics Working Group as a potential successor to the MIL-STD-1750A 16-bit processor for military applications. It is pointed out that there are a number of important performance issues associated with using high-order languages such as Ada
openaire   +1 more source

Instruction scheduling and transformation for a VLIW unified reduced instruction set computer/digital signal processor processor with shared register architecture

Concurrency and Computation: Practice and Experience, 2012
SUMMARYThe popularity of multimedia applications made them a major theme in embedded systems. The key component for supporting multimedia application well is embedded processor. Thus, we have designed and implemented an embedded processor, called UniDual processor, to achieve this objective.
Cheng‐Yu Lee, Min‐Chin Hung, Rong‐Guey Chang   +2 more
openaire   +1 more source

Reduced Instruction Set Computers — Grundprinzipien einer neuen Prozessorarchitektur

1986
Der Begriff “Reduced Instruction Set Computer” (RISC) fur eine Prozessorarchitektur auf der Basis stark vereinfachter, auf das Notwendigste reduzierter Befehlssatze wurde Anfang der 80er Jahre von David Patterson (University of California, Berkeley) gepragt, nachdem im IBM Forschungszentrum in Yorktown Heights schon einige Jahre an einer ...
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Built-in self test and a VLSI stack-frame reduced-instruction set computer (RISC) architecture

IEEE Conference on Aerospace and Electronics, 2002
The authors describe the construction of the SF2000 VLSI stack-frame RISC computer (a design based on the successful SF1 computer) and discuss the advanced methods, such as random pattern testing and design partitioning aids, used in the construction of the on-chip BIST (built-in self test) hardware in this three-chip computer. The SF2000 CPU chip will
C.-I.H. Chen, R. Dixon, R. Hohne, L. Peterson, R. Siferd   +4 more
openaire   +1 more source

RISC-V Instruction Set Architecture Extensions: A Survey

IEEE Access, 2023
Enfang Cui, Qian Wei
exaly  

Reduced Instruction Set Computing

, 1999
Vojin G. Oklobdzija
openalex   +1 more source

Reduced instruction set computers

2004
B. S. Chalk, A. T. Carter, R. W. Hind
openaire   +1 more source

Reduced Instruction Set Computing

, 2007
Vojin G. Oklobdzija
openalex   +1 more source