Results 221 to 230 of about 13,809 (235)

The RISC-V instruction set

2013 IEEE Hot Chips 25 Symposium (HCS), 2013
Andrew Waterman, Yunsup Lee, Rimas Avizienis, Henry Cook, David Patterson, Krste Asanovic   +5 more
openaire   +1 more source

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

IEEE Journal of Solid-State Circuits, 2016
Brian Zimmer, Yunsup Lee, Alberto Puggelli   +2 more
exaly  

Návrh superskalárního RISC-V procesoru

This thesis deals with designing and implementing a superscalar RISC-V processor microarchitecture focused on environments with constrained resources. For that, the microarchitecture exposes a dual-issue seven-stage pipeline with in-order instruction execution. It is described in SystemVerilog and can be easily simulated on a computer.
openaire   +1 more source

RISC-V based virtual prototype: An extensible and configurable platform for the system-level

Journal of Systems Architecture, 2020
Vladimir Herdt, Pascal Pieper
exaly  

An Agile Approach to Building RISC-V Microprocessors

IEEE Micro, 2016
Yunsup Lee, Andrew Waterman, Henry Cook
exaly  

A Reconfigurable Convolutional Neural Network-Accelerated Coprocessor Based on RISC-V Instruction Set

Electronics (Switzerland), 2020
exaly  

Building a RISC-V Processor

2023
openaire   +1 more source

Characterizing a RISC-V SRAM-based FPGA implementation against Single Event Upsets using fault injection

Microelectronics Reliability, 2017
Alexis Ramos, Juan Antonio Maestro
exaly  

Testing Your RISC-V Processor

2023
openaire   +1 more source

Post-Quantum Signatures on RISC-V with Hardware Acceleration

Transactions on Embedded Computing Systems
Patrick Karl, , Tim Fritzmann
exaly