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A lightweight ISE for ChaCha on RISC-V
2021 IEEE 32nd International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2021ChaCha is a high-throughput stream cipher designed with the aim of ensuring high-security margins while achieving high performance on software platforms. RISC-V, an emerging, free, and open Instruction Set Architecture (ISA) is being developed with many instruction set extensions (ISE).
Ben Marshall +2 more
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A Compiler Comparison in the RISC-V Ecosystem
2020 International Conference on Omni-layer Intelligent Systems (COINS), 2020The GNU Compiler Collection (GCC) is the traditional compiler for most embedded systems, since it supports many different instruction set architectures (ISA) in its back-end. GCC has also been the first compiler that supported the RISC-V ISA. Since a while Clang/LLVM has gained more and more interest in the embedded software community. Recently, RISC-V
Mehrdad Poorhosseini +2 more
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RISC-V Extension for Lightweight Cryptography
2020 23rd Euromicro Conference on Digital System Design (DSD), 2020Lightweight Cryptography (LWC) is suitable for IoTs which require a high level of security while keeping a low complexity. Many lightweight cryptographic algorithms have been proposed to satisfy these requirements. But there is currently no emerging standard concerning the symmetric block ciphering, as every algorithm has its own advantage.
Etienne Tehrani +3 more
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The chip crisis in early 2020 clearly revealed how dependent German and European industry was on the supply chains for microelectronic components. Despite experts repeatedly emphasising the importance of microelectronics to Europe’s capacity for innovation, shortages occurred which threatened major industrial sectors.
Qusay F. Hassan, Assim Sagahyroon
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Qusay F. Hassan, Assim Sagahyroon
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RISC-V2: A Scalable RISC-V Vector Processor
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020Machine learning adoption has seen a widespread bloom in recent years, with neural network implementations being at the forefront. In light of these developments, vector processors are currently experiencing a resurgence of interest, due to their inherent amenability to accelerate data-parallel algorithms required in machine learning environments.
Karyofyllis Patsidis +3 more
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High-Performance RISC-V Emulation
2020RISC-V is an open ISA that has been calling the attention worldwide by its fast growth and adoption. It is already supported by GCC, Clang and the Linux Kernel. However, none of the currently available RISC-V emulators are capable of providing good, near-native, emulation performance.
Leandro Lupori +2 more
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2023 International Conference on IC Design and Technology (ICICDT), 2023
Sam Rogan, Yoshihito Kondo
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Sam Rogan, Yoshihito Kondo
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The Scale4Edge RISC-V Ecosystem
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022Wolfgang Ecker +26 more
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Modeling RISC-V Processor in IP-XACT
2018 21st Euromicro Conference on Digital System Design (DSD), 2018IP-XACT is the most used standard in IP (Intellectual Property) integration. It is intended as a language neutral golden reference, from which RTL and HW dependent SW is automatically generated. Despite its wide popularity in the industry, there are practically no public and open design examples for any part of the design flow from IP-XACT to synthesis.
Pekkarinen Esko, Hämäläinen Timo D.
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