Results 81 to 90 of about 9,109,748 (351)

HERO: Heterogeneous Embedded Research Platform for Exploring RISC-V Manycore Accelerators on FPGA

, 2017
Heterogeneous embedded systems on chip (HESoCs) co-integrate a standard host processor with programmable manycore accelerators (PMCAs) to combine general-purpose computing with domain-specific, efficient processing capabilities.
Benini, Luca, Capotondi, Alessandro, Kurth, Andreas, Marongiu, Andrea, Vogel, Pirmin   +4 more
core   +1 more source

Development of Classroom Tools for a RISC-V Embedded System [PDF]

, 2022
RISC-V is an open-source instruction set that has been gaining popularity in recent years, and, with support from large chip manufacturers like Intel and the benefits of its open-source nature, RISC-V devices are likely to continue gaining momentum. Many
Phillips, Lucas
core   +1 more source

Audio Denoising Coprocessor Based on RISC-V Custom Instruction Set Extension

Acoustics, 2022
As a typical active noise control algorithm, Filtered-x Least Mean Square (FxLMS) is widely used in the field of audio denoising. In this study, an audio denoising coprocessor based on Retrenched Injunction System Computer-V (RISC-V), a custom ...
Jun Yuan, Qiang Zhao, Wei Wang, Xiangsheng Meng, Jun Li, Qin Li   +5 more
doaj   +1 more source

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices [PDF]

ACM International Conference on Computing Frontiers
RISC-V cores have gained a lot of popularity over the last few years. However, being quite a recent and novel technology, there is still a gap in the availability of comprehensive simulation frameworks for RISC-V that cover both the functional and extra ...
Mohamed Amine Hamdi, Giovanni Pollo, Matteo Risso, Germain Haugou, Alessio Burrello, Enrico Macii, M. Poncino, S. Vinco, D. J. Pagliari   +8 more
semanticscholar   +1 more source

Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip

Electronics, 2023
Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables the implementation and customization of the processor features to increase ...
D. Santos, André M. P. Mattos, D. Melo, L. Dilillo   +3 more
semanticscholar   +1 more source

Machine Learning‐Enabled Polymer Discovery for Enhanced Pulmonary siRNA Delivery

Advanced Functional Materials, EarlyView.
This study provides an efficient approach to train a machine learning model by merging heterogeneous literature data to predict suitable polymers for siRNA delivery. Without the need for extensive laboratory synthesis, the machine learning enabled a virtual screening and successfully predicted a polymer that is validated for effective gene silencing in
Felix Sieber‐Schäfer, Min Jiang, Adrian Kromer, Anny Nguyen, Müge Molbay, Simone Pinto Carneiro, David Jürgens, Gerald Burgstaller, Bastian Popper, Benjamin Winkeljann, Olivia Monika Merkel   +10 more
wiley   +1 more source

Digital Signal Processing Accelerator for RISC-V [PDF]

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019
In this work, we present a configurable accelerator for the RISC-V processor oriented to digital signal processing applications for energy efficient Internet-of-Things devices. The supported operations in the accelerator are addition, multiplication, and linear combination.
Calicchia L., Ciotoli V., Cardarilli G. C., Di Nunzio L., Fazzolari R., Nannarelli A., Re M.   +6 more
openaire   +2 more sources

From FPGA to ASIC: A RISC-V processor experience [PDF]

, 2019
This work document a correct design flow using these tools in the Lagarto RISC- V Processor and the RTL design considerations that must be taken into account, to move from a design for FPGA to design for ...
Rojas Morales, Carlos
core   +1 more source

Design of System On Chip with RISC-V processor for USI graphical pen controller [PDF]

, 2023
Tato diplomová práce se zabývá RTL návrhem a implementací systému systému na čipu na procesorové platformě RISC-V pro USI ovladač grafického pera. Současný SoC ovladače pera založeného na CoolRISC je analyzován a na základě této analýzy je vytvořen ...
Martin Stahl
core  

Comprehensive analysis of energy efficiency and performance of ARM and RISC-V SoCs

Journal of Supercomputing
Over the past few years, ARM has been the dominant player in embedded systems and System-on-Chips (SoCs). With the emergence of hardware platforms based on the RISC-V architecture, a practical comparison focusing on their energy efficiency and ...
Daniel Suárez, F. Almeida, V. Blanco
semanticscholar   +1 more source