Results 41 to 50 of about 582,151 (290)

A 74-dB Dynamic-Range 625-kHz Bandwidth Second-Order Noise-Shaping SAR ADC Utilizing a Temperature-Compensated Dynamic Amplifier and a Digital Mismatch Calibration

IEEE Access, 2021
This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to ...
Jae Sik Yoon, Jiyoon Hong, Hyungil Chae, Jintae Kim   +3 more
doaj   +1 more source

Offset-calibration with Time-Domain Comparators Using Inversion-mode Varactors [PDF]

, 2019
This paper presents a differential time-domain comparator formed by two voltage controlled delay lines, one per input terminal, and a binary phase detector for comparison solving.
Delgado Restituto, Manuel, Fiorelli, Rafaella, Rodríguez Vázquez, Ángel Benito   +2 more
core   +1 more source

PixFEL: development of an X-ray diffraction imager for future FEL applications [PDF]

, 2017
A readout chip for diffraction imaging applications at new generation X-ray FELs (Free Electron Lasers) has been designed in a 65 nm CMOS technology. It consists of a 32 × 32 matrix, with square pixels and a pixel pitch of 110 µm.
Battignani, Giovanni, Benkechkache, Mohamed El Amine, Bettarini, Stefano, Casarosa, Giulia, Dalla Betta, Gian-Franco, Fabris, Lorenzo, Forti, Francesco, Giorgi, Marcello, Grassi, Marco, Lodola, Luca, Malcovati, Piero, Manghisoni, Massimo, Morsani, Fabio, Paladino, Antonio, Pancheri, Lucio, Paoloni, Eugenio, Ratti, Lodovico, Re, Valerio, Rizzo, Giuliana, Traversi, Gianluca, Vacchi, Carla, Verzellesi, G.   +21 more
core   +1 more source

Noise shaping in SAR ADC

Facta universitatis - series: Electronics and Energetics, 2020
The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels.
Dmitry Osipov, Aleksandr Gusev, Vitaly Shumikhin, Steffen Paul   +3 more
openaire   +2 more sources

A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET

IEEE Access, 2021
This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system.
Yan Zheng, Jingchao Lan, Fan Ye, Junyan Ren   +3 more
doaj   +1 more source

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS [PDF]

, 2017
In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the ...
Andrei, Alexandru, Ballini, Marco, Mitra, Srinjoy, Mora Lopez, Carolina, Musa, Silke, Putzeys, Jan, Raducanu, Bogdan Cristian, Rochus, Veronique, Severi, Simone, Van Helleputte, Nick, Van Hoof, Chris, Vandebriel, Roeland, Wang, Shiwei, Yazicioglu, Refet Firat   +13 more
core   +1 more source

Low-power SAR ADCs: trends, examples and future

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019
With the development of mobile devices and Internet-of-Things,the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work,we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations,it can be shown why
Harpe, Pieter, Li, Hanyue, Shen, Yuting
openaire   +2 more sources

High-Resolution ADCs Design in Image Sensors [PDF]

, 2018
This paper presents design considerations for high-resolution and high-linearity ADCs for biomedical imaging ap-plications. The work discusses how to improve dynamic spec-ifications such as Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and ...
Cen, Yuanjun, Fan, Hua, Feng, Quanyuan, Heidari, Hadi, Hu, Daqian, Li, Dagang, Maloberti, Franco, Yang, Jingxuan   +7 more
core   +1 more source

Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC

SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology, 2021
The paper proposes an analog to digital converter (ADC) which is reconfigurable and it consists of successive approximation register (SAR) ADC and SAR-Assisted pipeline ADC that can improve the resolution and conversion time based on the application. This reconfigurable ADC is designed to obtain an 8-bit resolution with low conversion time, a 16-bit (8-
Harsh Sawardekar, Jayamala Adsul
openaire   +1 more source

Floating capacitor switching SAR ADC

Electronics Letters, 2011
An energy-efficiency floating-capacitor switching (FCS) scheme is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By rearranging the switching order from the smallest capacitor to the largest one, the switching energy can be significantly reduced, especially in the first several DAC switchings.
C.H. Kuo, C.E. Hsieh
openaire   +1 more source