Results 41 to 50 of about 17,773 (197)
A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET
IEEE Access, 2021 This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system.
Yan Zheng +3 more
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A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS [PDF]
, 2017 In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the ...
Andrei, Alexandru +13 more
core +1 more source
Low-power SAR ADCs: trends, examples and future
ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019 With the development of mobile devices and Internet-of-Things,the demand for low-power circuits has been growing rapidly. The Analog-to-Digital Converter (ADC) is a key building block in these systems. In this work,we review the progress of low-power ADCs over the years in terms of performance and limitations. From these limitations,it can be shown why
Harpe, Pieter, Li, Hanyue, Shen, Yuting
openaire +2 more sources
FMCW rail-mounted SAR: Porting spotlight SAR imaging from MATLAB to FPGA [PDF]
, 2014 In this work, a low-cost laptop-based radar platform derived from the MIT open courseware has been implemented. It can perform ranging, Doppler measurement and SAR imaging using MATLAB as the processor.
Gray, D., Le Kernec, J., Melnikov, A.
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Reconfigurable Successive Approximation Register ADC and SAR-Assisted Pipeline ADC
SAMRIDDHI : A Journal of Physical Sciences, Engineering and Technology, 2021 The paper proposes an analog to digital converter (ADC) which is reconfigurable and it consists of successive approximation register (SAR) ADC and SAR-Assisted pipeline ADC that can improve the resolution and conversion time based on the application. This reconfigurable ADC is designed to obtain an 8-bit resolution with low conversion time, a 16-bit (8-
Harsh Sawardekar, Jayamala Adsul
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Performances of multitones for ultra-wideband software-defined radar [PDF]
, 2017 From the literature review, it is apparent that there is a gap in quantifying the performances of multitone waveforms specifically for radar applications and experimental results are not commonly found.
Le Kernec, Julien, Romain, Olivier
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Floating capacitor switching SAR ADC
Electronics Letters, 2011 An energy-efficiency floating-capacitor switching (FCS) scheme is proposed for successive approximation register (SAR) analogue-to-digital converters (ADCs). By rearranging the switching order from the smallest capacitor to the largest one, the switching energy can be significantly reduced, especially in the first several DAC switchings.
C.H. Kuo, C.E. Hsieh
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Combined architecture of an analog-to-digital converter with balanced throughput–cost trade-off
Радіоелектронні і комп'ютерні системиThe object of research in this article is a combined architecture of analog-to-digital converters (ADCs), which is built by integrating a low-resolution flash ADC with a successive approximation register (SAR) ADC.
Oleksiy Azarov +4 more
doaj +1 more source
IEEE Access, 2020 An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications.
Deeksha Verma +10 more
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Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering
ChipsThe noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs.
Zhaoyang Shen, Shiheng Yang, Jiaxin Liu
doaj +1 more source