Results 21 to 30 of about 2,350 (180)
Electronics Letters, 2022 Noise‐shaping (NS) successive approximation register (SAR) analogue‐to‐digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications.
Weihao Wang +3 more
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A ZOOM ADC for Protable Gyroscope
Journal of Harbin University of Science and Technology, 2020 This design is a high precision ZOOM analogtodigital converter (ADC) presented for using in microelectromechanical systems (MEMS) gyroscope sensors The structure consists of a successive approximation (SAR) ADC and a Sigma Delta modulator The coarse ...
MEI Jinshuo, CUI Tianbao
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Design and Implementation of SAR ADC
Journal of Computers, 2011 The successive approximation register analog to digital converter (SAR ADC) technique is not yet mature in China mainly because of the imperfect analog module of the SAR ADC. The purpose of this design was to optimize the analog module by designing and making a 8-bit 1MHz SAR ADC and testing a 12-bit SAR ADC theoretically and by simulation.
Weibin Wu 0001 +5 more
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Behavioral Modeling of SAR ADCs in Simulink
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018 This paper presents a toolbox for the behavioral simulation of SAR ADCs in Simulink®. The models include the most limiting circuit effects such as sampled thermal noise, capacitor mismatch, finite settling, comparator noise and offset. A user friendly interface is also included to allow study and high-level design of SAR ADCs, which is illustrated by ...
Gerardo Molina Salgado +4 more
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IEEE Access, 2021 This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to ...
Jae Sik Yoon +3 more
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A 12-bit 100MS/s SAR ADC With Equivalent Split-Capacitor and LSB-Averaging in 14-nm CMOS FinFET
IEEE Access, 2021 This paper presents an energy-saving and high-resolution successive approximation register (SAR) analog-to-digital converter (ADC) with 14-nm CMOS FinFET technology for wireless communication system.
Yan Zheng +3 more
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Combined architecture of an analog-to-digital converter with balanced throughput–cost trade-off
Радіоелектронні і комп'ютерні системиThe object of research in this article is a combined architecture of analog-to-digital converters (ADCs), which is built by integrating a low-resolution flash ADC with a successive approximation register (SAR) ADC.
Oleksiy Azarov +4 more
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Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering
ChipsThe noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs.
Zhaoyang Shen, Shiheng Yang, Jiaxin Liu
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Design and Implementation of High Speed and Low Power 12-Bit SAR ADC Using 22nm FinFET
Iranian Journal of Electrical and Electronic Engineering, 2022 Successive approximation register (SAR) analog to digital converter (ADC) architecture comprises submodules such as comparator, digital to analog converters (DAC), and SAR logic.
G. Vasudeva, B. V. Uma
doaj
IEEE Access, 2020 An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications.
Deeksha Verma +10 more
doaj +1 more source