Results 21 to 30 of about 207,759 (231)
IET Circuits, Devices and Systems, 2022 Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong +8 more
doaj +1 more source
Electronics Letters, 2022 Noise‐shaping (NS) successive approximation register (SAR) analogue‐to‐digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications.
Weihao Wang +3 more
doaj +1 more source
A ZOOM ADC for Protable Gyroscope
Journal of Harbin University of Science and Technology, 2020 This design is a high precision ZOOM analogtodigital converter (ADC) presented for using in microelectromechanical systems (MEMS) gyroscope sensors The structure consists of a successive approximation (SAR) ADC and a Sigma Delta modulator The coarse ...
MEI Jinshuo, CUI Tianbao
doaj +1 more source
Bandpass ΔΣ ADC using pipelined SAR ADC [PDF]
Electronics Letters, 2020 This Letter proposes a second‐order bandpass ΔΣ ADC using a pipelined successive‐approximation‐register (SAR) ADC as an internal quantiser. The second‐order bandpass noise‐shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure.
S. Oh, K. Kim, H. Chae
openaire +1 more source
, 2019 ADC ArcheoProjecten heeft in augustus 2018 een inventariserend veldonderzoek uitgevoerd op de locatie Mary Zeldenrustweg 18 te Leiden. De aanleiding van het onderzoek is de voorgenomen bouw van woningen.
Huizer, J. (ADC ArcheoProjecten)
core +2 more sources
A Single-Amplifier Dual-Residue Pipelined-SAR ADC
, 2021 This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the
Min-Jae Seo
core +1 more source
Design and Implementation of SAR ADC
Journal of Computers, 2011 The successive approximation register analog to digital converter (SAR ADC) technique is not yet mature in China mainly because of the imperfect analog module of the SAR ADC. The purpose of this design was to optimize the analog module by designing and making a 8-bit 1MHz SAR ADC and testing a 12-bit SAR ADC theoretically and by simulation.
Weibin Wu 0001 +5 more
openaire +2 more sources
IEEE Access, 2021 This paper presents the design of a 2nd-order Noise-Shaping (NS) Successive-Approximation-Register (SAR) Analog-to-Digital Converter (ADC) employing a cascade of temperature-compensated dynamic amplifier and a ring amplifier in the feedback path to ...
Jae Sik Yoon +3 more
doaj +1 more source
Behavioral Modeling of SAR ADCs in Simulink
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018 This paper presents a toolbox for the behavioral simulation of SAR ADCs in Simulink®. The models include the most limiting circuit effects such as sampled thermal noise, capacitor mismatch, finite settling, comparator noise and offset. A user friendly interface is also included to allow study and high-level design of SAR ADCs, which is illustrated by ...
Gerardo Molina Salgado +4 more
openaire +2 more sources
Combined architecture of an analog-to-digital converter with balanced throughput–cost trade-off
Радіоелектронні і комп'ютерні системиThe object of research in this article is a combined architecture of analog-to-digital converters (ADCs), which is built by integrating a low-resolution flash ADC with a successive approximation register (SAR) ADC.
Oleksiy Azarov +4 more
doaj +1 more source