Results 11 to 20 of about 2,350 (180)
Desain ADC SAR 10-Bit Dua Kanal Simultan menggunakan Board FPGA Altera DE10
Jurnal Elkomika, 2022 ABSTRAK Desain arsitektur ADC (Analog to Digital Converter) multi kanal simultan pada perangkat kontroller dapat mengurangi jumlah intruksi (task) program yang harus dijalankan oleh mikroprosessor dan dapat digunakan untuk membentuk pengukuran simultan.
MUHAMMAD ULIN NUHA +2 more
doaj +1 more source
A 14.5-Bit ENOB, 10MS/s SAR-ADC With 2nd Order Hybrid Passive-Active Resonator Noise Shaping
IEEE Access, 2022 A new 2nd order noise shaping (NS) based successive approximation register (SAR) ADC is presented in this paper. In comparison to earlier research, this paper considers hybrid passive-active integrators to compensate for the phase error of the passive ...
Ximing Fu, Kamal El-Sankary
doaj +1 more source
Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications
Active and Passive Electronic Components, 2023 This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison.
Kawther I. Arafa +4 more
doaj +1 more source
Electronics Letters, 2022 The authors present a low‐power area‐efficient subarray beamforming receiver (RX) structure for a miniaturized 3‐D ultrasound imaging system. Given that the delay‐and‐sum (DAS) and digitization functions consume most of the area and power in the receiver,
Seungah Lee, Soohyun Yun, Joonsung Bae
doaj +1 more source
A 12 bit 76MS/s SAR ADC with a Capacitor Merged Technique in 0.18µm CMOS Technology [PDF]
Journal of Electrical and Computer Engineering Innovations, 2017 A new high-resolution and high-speed fully differential Successive Approximation Register (SAR) Analog to Digital Converter (ADC) based on Capacitor Merged Technique is presented in this paper.
S. Mahdavi
doaj +1 more source
Implementation of a digital trim scheme for SAR ADCs [PDF]
Advances in Radio Science, 2013 Successive approximation register (SAR) analog-to-digital Converters (ADC) are based on a capacitive digital-to-analog converter (CDAC) (McCreary and Gray, 1975).
J. Bialek +5 more
doaj +1 more source
Bandpass ΔΣ ADC using pipelined SAR ADC [PDF]
Electronics Letters, 2020 This Letter proposes a second‐order bandpass ΔΣ ADC using a pipelined successive‐approximation‐register (SAR) ADC as an internal quantiser. The second‐order bandpass noise‐shaping is achieved by utilising the residue signal after SAR conversion and inherent delay existing in a pipelined structure.
S. Oh, K. Kim, H. Chae
openaire +1 more source
Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs
IEEE Open Journal of Circuits and Systems, 2021 This paper presents the sampling and comparator speed-enhancement techniques for SAR ADCs under near-threshold supply voltages. The proposed level-shifted boosting circuit generates sharp falling edges for the sampling clock, which is found a key factor ...
Bojun Hu +7 more
doaj +1 more source
IEEE Access, 2021 A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed.
Hsuan-Lun Kuo, Chih-Wen Lu, Poki Chen
doaj +1 more source
IET Circuits, Devices and Systems, 2022 Mismatch in the binary‐weighted capacitive digital‐to‐analog converter (DAC) greatly affects the linearity of the successive‐approximation‐register (SAR) ADC by deteriorating the total harmonic distortion (THD).
Li Dong +8 more
doaj +1 more source