Results 51 to 60 of about 582,151 (290)

Combined architecture of an analog-to-digital converter with balanced throughput–cost trade-off

Радіоелектронні і комп'ютерні системи
The object of research in this article is a combined architecture of analog-to-digital converters (ADCs), which is built by integrating a low-resolution flash ADC with a successive approximation register (SAR) ADC.
Oleksiy Azarov, Oleksandr Dudnyk, Maksym Obertiukh, Oleksandr Lukashuk, Oleksandr Murashchenko   +4 more
doaj   +1 more source

FMCW rail-mounted SAR: Porting spotlight SAR imaging from MATLAB to FPGA [PDF]

, 2014
In this work, a low-cost laptop-based radar platform derived from the MIT open courseware has been implemented. It can perform ranging, Doppler measurement and SAR imaging using MATLAB as the processor.
Gray, D., Le Kernec, J., Melnikov, A.
core   +1 more source

Performances of multitones for ultra-wideband software-defined radar [PDF]

, 2017
From the literature review, it is apparent that there is a gap in quantifying the performances of multitone waveforms specifically for radar applications and experimental results are not commonly found.
Le Kernec, Julien, Romain, Olivier
core   +3 more sources

An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier

IEEE Open Journal of the Solid-State Circuits Society, 2021
The Noise-Shaping (NS) SAR is an attractive new ADC architecture that emerged in the last decade. It combines the advantages of the SAR and the DSM architectures.
Lu Jie, Xiyuan Tang, Jiaxin Liu, Linxiao Shen, Shaolan Li, Nan Sun, M. Flynn   +6 more
semanticscholar   +1 more source

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

Chips
The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs.
Zhaoyang Shen, Shiheng Yang, Jiaxin Liu
doaj   +1 more source

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

IEEE Access, 2020
An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications.
Deeksha Verma, Khuram Shehzad, Danial Khan, Qurat Ul Ain, Sung Jin Kim, Dongsoo Lee, Younggun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee   +10 more
doaj   +1 more source

Compact personal distributed wearable exposimeter [PDF]

, 2015
A compact wearable personal distributed exposimeter (PDE) is proposed, sensing the power density of incident radio frequency (RF) fields on the body of a human.
Joseph, Wout, Knockaert, Jos, Rogier, Hendrik, Thielens, Arno, Van Torre, Patrick, Vanveerdeghem, Peter   +5 more
core   +1 more source

A 590 µW, 106.6 dB SNDR, 24 kHz BW Continuous-Time Zoom ADC with a Noise-Shaping 4-bit SAR ADC

European Solid-State Circuits Conference, 2022
This paper presents a continuous-time zoom ADC for audio applications. It combines a 4-bit noise-shaping coarse SAR ADC and a fine delta-sigma modulator with a tail-resistor linearized OTA for improved linearity, energy efficiency, and handling of out-of-
Shubham Mehrotra, E. Eland, Shoubhik Karmakar, Angqi Liu, Burak Gönen, M. Bolatkale, R. V. Veldhoven, K. Makinwa   +7 more
semanticscholar   +1 more source

11 b 200 MS/s 28‐nm CMOS 2b/cycle successive‐approximation register analogue‐to‐digital converter using offset‐mismatch calibrated comparators

Electronics Letters, 2023
This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive‐approximation register (SAR) analogue‐to‐digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of ...
Jaehyuk Lee, Junho Boo, Junsang Park, Taiji An, Heewook Shin, Youngjae Cho, Michael Choi, Jinwook Burm, Gilcho Ahn, Seunghoon Lee   +9 more
doaj   +1 more source

A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

IET Circuits, Devices and Systems, 2021
A novel switched‐capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta‐sigma modulator
Sreenivasulu Polineni, Rekha S., M. S. Bhat   +2 more
doaj   +1 more source