Results 21 to 30 of about 115 (112)

Jitter-Quantizing-Based TRNG Robust Against PVT Variations

open access: yesIEEE Access, 2020
Security is critical to the growing popularity of the Internet of Things(IoT), and true random number generator (TRNG) plays an increasingly important role in information security systems.
Yingchun Lu   +7 more
doaj   +1 more source

Designing fault-tolerant techniques for SRAM-based FPGAs [PDF]

open access: yesIEEE Design and Test of Computers, 2004
FPGAs have become prevalent in critical applications in which transient faults can seriously affect the circuit's operation. We present a fault tolerance technique for transient and permanent faults in SRAM-based FPGAs. This technique combines duplication with comparison (DWC) and concurrent error detection (CEO) to provide a highly reliable circuit ...
Fernanda Lima Kastensmidt   +4 more
openaire   +1 more source

Custom Scrubbing for Robust Configuration Hardening in Xilinx FPGAs

open access: yesInstruments, 2019
The usage of SRAM-based Field Programmable Gate Arrays on High Energy Physics detectors is mostly limited by the sensitivity of these devices to radiation-induced upsets in their configuration.
Raffaele Giordano   +3 more
doaj   +1 more source

A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays

open access: yesSensors
Aerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space applications are highly susceptible to single event effects, leading to soft errors in FPGAs.
Weihang Wang   +4 more
doaj   +1 more source

ACME: A Tool to Improve Configuration Memory Fault Injection in SRAM-Based FPGAs

open access: yesIEEE Access, 2019
Circuits in harsh environments, as space, tend to suffer severe problems caused by radiation. In this scenario, where the behavior of the system can be jeopardized, it is critical to produce fault tolerant circuits that can operate correctly.
Luis Alberto Aranda   +2 more
doaj   +1 more source

AC_ICAP: A Flexible High Speed ICAP Controller

open access: yesInternational Journal of Reconfigurable Computing, 2015
The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs).
Luis Andres Cardona, Carles Ferrer
doaj   +1 more source

Optimal Partial Reconfiguration for Permanent Fault Recovery on SRAM-Based FPGAs in Space Mission

open access: yesAdvances in Mechanical Engineering, 2013
In this paper, we present a technique to maximize the lifetime of SRAM-based FPGAs in space mission. We focus on recovering permanent faults induced by SEE (single-events effect).
Jie Zhang, Yong Guan, Chunjing Mao
doaj   +1 more source

Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks

open access: yesAdvanced Electronic Materials, EarlyView.
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley   +1 more source

A Scalable and Resource‐Efficient Pipelined p‐Computer for Probabilistic Ising Machines

open access: yesAdvanced Intelligent Systems, EarlyView.
(a) Block diagram of the portfolio optimization problem: given M assets, the goal is to determine the optimal weights w that maximize the expected return (based on the mean historical assets return u), while minimizing the risk, quantified by the assets covariance matrix S.
Deborah Volpe   +9 more
wiley   +1 more source

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

open access: yesInternational Journal of Reconfigurable Computing, 2008
This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design.
Y. Guillemenet   +3 more
doaj   +1 more source

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