Results 1 to 10 of about 37,708 (227)
A Review on Soft Error Correcting Techniques of Aerospace-Grade Static RAM-Based Field-Programmable Gate Arrays [PDF]
SensorsAerospace-grade SRAM-based field-programmable gate arrays (FPGAs) used in space applications are highly susceptible to single event effects, leading to soft errors in FPGAs.
Weihang Wang +4 more
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Impact of Fabrication Defects on FPGA Logic Using Memristor-Based Memory Cells [PDF]
MicromachinesMemristor-based configuration memory offers an alternative solution to the volatility and large area overhead of conventional Static Random Access Memory (SRAM)-based FPGA configuration memory.
Jonas Schoenen +10 more
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The Design of a Dynamic Configurable Packet Parser Based on FPGA [PDF]
Micromachines, 2023 To meet the evolving demands of programmable networks and address the limitations of traditional fixed-type protocol parsers, we propose a dynamic and configurable low-latency parser implemented on an FPGA.
Ying Sun, Zhichuan Guo
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Soft error mitigation and recovery of SRAM-based FPGAs using brain-inspired hybrid-grained scrubbing mechanism [PDF]
Frontiers in Computational Neuroscience, 2023 Soft error has increasingly become a critical concern for SRAM-based field programmable gate arrays (FPGAs), which could corrupt the configuration memory that stores configuration data describing the custom-designed circuit architecture. To mitigate this
Yu Xie +3 more
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A superior ultrafast parallel BMAS architecture for high-resolution medical ultrasound imaging [PDF]
Scientific ReportsThe proposed work aims to design, a novel ultrafast–parallel beamformer core for medical ultrasound imaging systems that is superior in performance compared to preceding beamformers. The architecture is aimed at achieving high-resolution images using 128
Sreejeesh SG +2 more
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Secure ECDSA SRAM-PUF Based on Universal Single/Double Scalar Multiplication Architecture [PDF]
MicromachinesPhysically unclonable functions (PUFs) are crucial for enhancing cybersecurity by providing unique, intrinsic identifiers for electronic devices, thus ensuring their authenticity and preventing unauthorized cloning.
Jingqi Zhang +8 more
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Efficiency of Priority Queue Architectures in FPGA
Journal of Low Power Electronics and Applications, 2022 This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC.
Lukáš Kohútka
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Soft Error Mitigation for SRAM-Based FPGAs [PDF]
23rd IEEE VLSI Test Symposium (VTS'05), 2005 FPGA-based designs are more susceptible to single-event up-sets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits.
Ghazanfar Asadi, Mehdi Baradaran Tahoori
openaire +1 more source
Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs
IEEE Access, 2021 There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory
Luis Alberto Aranda +3 more
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Nantong Daxue xuebao. Ziran kexue ban, 2020 With the wide application of FPGA(field programmable gate array) based on the SRAM(static randomaccess memory) in the aerospace field, the probability of SEU(single event upset) increases gradually while the FPGAs are exposed in irradiation environment ...
XIE Da;DONG Yiping;WANG Lan;CAO Jinde;GUO Junjie
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