Results 1 to 10 of about 119 (117)
Efficiency of Priority Queue Architectures in FPGA
Journal of Low Power Electronics and Applications, 2022 This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC.
Lukáš Kohútka
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Soft Error Mitigation for SRAM-Based FPGAs [PDF]
23rd IEEE VLSI Test Symposium (VTS'05), 2005 FPGA-based designs are more susceptible to single-event up-sets (SEUs) compared to ASIC designs, since SEUs in configuration bits of FPGAs result in permanent errors in the mapped design. Moreover, the number of sensitive configuration bits is two orders of magnitude more than user bits in typical FPGA-based circuits.
Ghazanfar Asadi, Mehdi Baradaran Tahoori
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Reliability Analysis of ASIC Designs With Xilinx SRAM-Based FPGAs
IEEE Access, 2021 There are many platforms and tools based on field-programmable gate array (FPGA) devices oriented to facilitate the reliability estimation of digital designs, but they are usually focused only on configuration memory errors since the configuration memory
Luis Alberto Aranda +3 more
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Nantong Daxue xuebao. Ziran kexue ban, 2020 With the wide application of FPGA(field programmable gate array) based on the SRAM(static randomaccess memory) in the aerospace field, the probability of SEU(single event upset) increases gradually while the FPGAs are exposed in irradiation environment ...
XIE Da;DONG Yiping;WANG Lan;CAO Jinde;GUO Junjie
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Efficient TCAM Design Based on Multipumping-Enabled Multiported SRAM on FPGA
IEEE Access, 2018 Ternary content-addressable memory (TCAM)-based search engines play an important role in networking routers. The search space demands of TCAM applications are constantly rising.
Inayat Ullah, Zahid Ullah, Jeong-A Lee
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A defect-tolerant cluster in a mesh SRAM-based FPGA [PDF]
2013 International Conference on Field-Programmable Technology (FPT), 2013 In this paper, we propose the implementation of multiple defect-tolerant techniques on an SRAM-based FPGA. These techniques include redundancy at both the logic block and intra-cluster interconnect. In the logic block, redundancy is implemented at the multiplexer level.
Ben Dhia, Arwa +8 more
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High speed digital filtering on SRAM-based FPGAs [PDF]
Proceedings of 7th International Conference on VLSI Design, 2002 Field programmable gate arrays (FPGAs) represent a very promising technology that attempts to provide the benefits of custom VLSI with low turn-around time. However, the applicability of this technology for serious DSP applications, that are compute-intensive and typically demand high throughput, has not yet been fully explored.
Giri, A +3 more
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Marmote SDR: Experimental Platform for Low-Power Wireless Protocol Stack Research
Journal of Sensor and Actuator Networks, 2013 Over the past decade, wireless sensor network research primarily relied on highly-integrated commercial off-the-shelf radio chips. The rigid silicon implementation of the radio stack restricted access to the lower layers; thus, research focused mainly on
Ákos Lédeczi +3 more
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Improved Performance of SRAM-Based True Random Number Generator by Leveraging Irradiation Exposure
Sensors, 2020 Encryption is an important step for secure data transmission, and a true random number generator (TRNG) is a key building block in many encryption algorithms. Static random-access memory (SRAM) chips can be easily available sources of true random numbers,
Xu Zhang +9 more
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Research and Evaluation on SEM-based FPGA Anti-SEU Solution
Yuanzineng kexue jishu, 2022 With the development of aerospace avionics, there is an increasing demand for high performance chips to handle data processing and transmission requirements.
SUN Yifan;BAI Liang;SHUANG Xiaochuan;TIAN Wenbo;YOU Hongjun
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