Results 31 to 40 of about 138 (136)

Review of Memristors for In‐Memory Computing and Spiking Neural Networks

Advanced Intelligent Systems, Volume 8, Issue 3, March 2026.
Memristors uniquely enable energy‐efficient, brain‐inspired computing by acting as both memory and synaptic elements. This review highlights their physical mechanisms, integration in crossbar arrays, and role in spiking neural networks. Key challenges, including variability, relaxation, and stochastic switching, are discussed, alongside emerging ...
Mostafa Shooshtari, Teresa Serrano‐Gotarredona, Bernabé Linares‐Barranco   +2 more
wiley   +1 more source

Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

International Journal of Reconfigurable Computing, 2017
In modern SRAM based Field Programmable Gate Arrays, a Look-Up Table (LUT) is the principal constituent logic element which can realize every possible Boolean function. However, this flexibility of LUTs comes with a heavy area penalty.
Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid   +5 more
doaj   +1 more source

Cryogenic Neuromorphic Synaptic Behavior in 180 nm Silicon Transistors for Emerging Computing Systems

Advanced Intelligent Systems, Volume 8, Issue 2, February 2026.
This study investigates the neuromorphic plasticity behavior of 180 nm bulk complementary metal oxide semiconductor (CMOS) transistors at cryogenic temperatures. The observed hysteresis data reveal a signature of synaptic behavior in CMOS transistors at 4 K.
Fiheon Imroze, Bhavani Yalagala, Naveen Kumar, Mostafa Elsayed, Meraj Ahmad, Robert Graham, Vihar Georgiev, Hadi Heidari, Martin Weides   +8 more
wiley   +1 more source

On the Use of Magnetic RAMs in Field-Programmable Gate Arrays

International Journal of Reconfigurable Computing, 2008
This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design.
Y. Guillemenet, L. Torres, G. Sassatelli, N. Bruchon   +3 more
doaj   +1 more source

Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design

IEEE Access, 2018
A physical unclonable function (PUF) is a promising security primitive which utilizes the manufacturing process variations to generate a unique unclonable digital fingerprint for a chip.
Yijun Cui, Chongyan Gu, Chenghua Wang, Maire O'Neill, Weiqiang Liu   +4 more
doaj   +1 more source

An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs

IEEE Access, 2020
Reconfigurable SRAM-based Field Programmable Gate Arrays (FPGAs) are everyday more attractive due to their high integration, performance, flexibility, and upgradability.
Ludovica Bozzoli, Luca Sterpone
doaj   +1 more source

An Integrated Real-Time FMCW Radar Baseband Processor in 40-nm CMOS

IEEE Access, 2023
In this paper, a pipelined frequency-modulated continuous-wave (FMCW) radar baseband processor applied to real-time applications is proposed and implemented in 40-nm CMOS technology.
Mohan Guo, Dixian Zhao, Qisong Wu, Jiarui Wu, Diwei Li, Peng Zhang   +5 more
doaj   +1 more source

FPGA Realization of a Novel Hyperchaos Augmented Image Encryption Algorithm

IET Computers &Digital Techniques, Volume 2026, Issue 1, 2026.
With the rapid growth of multimedia communication, protecting image data has become increasingly critical. This article proposes a novel 3‐stage hyperchaos‐based augmented image encryption technique (3SHAIET) that utilizes a three‐stage process with chaotic systems of increasing dimensionality (e.g., six‐dimensional [6D], 8D, and 9D) to enhance ...
Wassim Alexan, Noura H. Elshabasy, Eyad Mamdouh, Remas Osama, Mohamed A. Abd El Ghany, Dina El-Damak, Jim Harkin   +6 more
wiley   +1 more source

UASR‐A: An Efficient Edge Super‐Resolution Accelerator With Hardware‐Algorithm Co‐Design Techniques

Electronics Letters, Volume 62, Issue 1, January/December 2026.
Deploying high‐performance super‐resolution on resource‐constrained edge devices is difficult due to heavy computation and memory bandwidth limits. We propose a hardware software co‐design consisting of a lightweight unified‐attention super‐resolution network (UASR) network (ConvFormer with unified‐attention mixer [UA‐M] and reparameterized edge ...
Yuqiao Huang, Dihu Chen, Tao Su
wiley   +1 more source

Fine-grain leakage optimization in SRAM based FPGAs [PDF]

Proceedings of the 15th ACM Great Lakes symposium on VLSI, 2005
FPGAs are evolving at a rapid pace with improved performance and logic density. At the same time, trends in technology scaling makes leakage power a serious concern for designers. In this paper, we propose a hierarchical look-up table (LUT) structure for FPGAs to improve leakage power consumption.
Somsubhra Mondal, Seda Ogrenci Memik
openaire   +1 more source