Results 51 to 60 of about 37,708 (227)
FPGA Realization of a Novel Hyperchaos Augmented Image Encryption Algorithm
IET Computers &Digital Techniques, Volume 2026, Issue 1, 2026.With the rapid growth of multimedia communication, protecting image data has become increasingly critical. This article proposes a novel 3‐stage hyperchaos‐based augmented image encryption technique (3SHAIET) that utilizes a three‐stage process with chaotic systems of increasing dimensionality (e.g., six‐dimensional [6D], 8D, and 9D) to enhance ...
Wassim Alexan +6 more
wiley +1 more source
, 2009 Several practical issues associated with achieving effective impedance performance in the finger joint space and stable grasping on a five-fingered dexterous hand are investigated in this work.
Z. X. Xue +17 more
core +1 more source
Optimization Opportunities in RRAM-based FPGA Architectures [PDF]
, 2017 Static Random Access Memory (SRAM)-based routing multiplexers, whatever structure is employed, share a common limitation: their area, delay and power increase linearly with the input size.
De Micheli, Giovanni +5 more
core +1 more source
On the Use of Magnetic RAMs in Field-Programmable Gate Arrays
International Journal of Reconfigurable Computing, 2008 This paper describes the integration of field-induced magnetic switching (FIMS) and thermally assisted switching (TAS) magnetic random access memories in FPGA design.
Y. Guillemenet +3 more
doaj +1 more source
Ultra-Lightweight and Reconfigurable Tristate Inverter Based Physical Unclonable Function Design
IEEE Access, 2018 A physical unclonable function (PUF) is a promising security primitive which utilizes the manufacturing process variations to generate a unique unclonable digital fingerprint for a chip.
Yijun Cui +4 more
doaj +1 more source
An Optimized Frame-Driven Routing Algorithm for Reconfigurable SRAM-Based FPGAs
IEEE Access, 2020 Reconfigurable SRAM-based Field Programmable Gate Arrays (FPGAs) are everyday more attractive due to their high integration, performance, flexibility, and upgradability.
Ludovica Bozzoli, Luca Sterpone
doaj +1 more source
UASR‐A: An Efficient Edge Super‐Resolution Accelerator With Hardware‐Algorithm Co‐Design Techniques
Electronics Letters, Volume 62, Issue 1, January/December 2026.Deploying high‐performance super‐resolution on resource‐constrained edge devices is difficult due to heavy computation and memory bandwidth limits. We propose a hardware software co‐design consisting of a lightweight unified‐attention super‐resolution network (UASR) network (ConvFormer with unified‐attention mixer [UA‐M] and reparameterized edge ...
Yuqiao Huang, Dihu Chen, Tao Su
wiley +1 more source
Virtual Page‐Based Flash Translation Layer for Compressed Solid‐State Drives
Electronics Letters, Volume 62, Issue 1, January/December 2026.This letter introduces a virtual page‐based flash translation layer (VPFTL) addressing the asymmetric logical‐to‐physical mappings introduced by data compression in SSDs. By grouping multiple physically related pages into a single virtual page, VPFTL flexibly manages mappings while preserving performance.
Yifan Shen +5 more
wiley +1 more source
Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA
, 2014 International audienceAs device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits.
Adrien Blanchardon +7 more
core +1 more source
Detection of Unknown Radar Pulses Using Spiking Neural Networks
IET Radar, Sonar &Navigation, Volume 20, Issue 1, January/December 2026.This article proposes to use spiking neural networks (SNNs) to detect multiple pulses in observation windows from a superheterodyne receiver. The method is described from encoding to postprocessing. New metrics are introduced to compare the proposed detection method to the energy detector (ED), to a detection based on difference Of boxes (DOB) filters ...
Alexia Tachet +2 more
wiley +1 more source